Robust leaded molded packages and methods for forming the same

• US 7,122,884 B2
• Filed: 04/14/2003
• Issued: 10/17/2006
• Est. Priority Date: 04/16/2002
• Status: Expired due to Term

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Montayre, Lilith U., Manatad, Romel N., Cabahug, Elsie Agdon, Gestole, Marvin Rosalejos, Tumulak-Rios, Margie Sebial
• Primary Examiner(s): Cao, Phat X.
• Application Number:
  US10/413,668
• Publication Number:
  US 20030193080A1
• Time in Patent Office: 1,282 Days
• Field of Search: 257/672, 257/676, 257/728, 257/666
• US Class Current: 257/676
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/16245 the item being metallic
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 23/49562 for devices being provided for in H01L29/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01046 Palladium [Pd]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/01322 Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/1305 Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Abstract

A method for making a flip chip in a leaded molded package is disclosed. In some embodiments, the method includes using a leadframe structure including a die attach region and leads. The die attach region includes depressions proximate the inner portions of the leads, and an aperture in the die attach region. A semiconductor die is mounted to the die attach region. A molding material passes through the aperture and covers the first surface of the semiconductor die and the die attach region.

Claims

1. A semiconductor package comprising:

(a) a semiconductor die including a first side and a second side, wherein the semiconductor die further includes a bond pad at the first side, the bond pad comprising an uneven surface;

(b) a leadframe structure comprising (i) a substantially planar die attach region, and (ii) a plurality of leads extending away from the die attach region;

(c) a plurality of solder structures between the semiconductor die and the leadframe structure and coupling the die attach region to the semiconductor die;

(d) a depression formed in the leadframe structure, the depression being between the one of the solder structures in the plurality of solder structures, and one of the leads in the plurality of leads, and wherein the depression is formed at an edge region of the die attach region; and

(e) a molding material covering the die attach region of the leadframe structure, the plurality of solder structures, and the first side of the semiconductor die,

wherein the leads in the plurality of leads extend laterally away from and outside of the molding material, and

wherein the solder structures are on the die attach pad and wherein the die attach pad includes a portion that is between and bridges the solder structures.

2. The semiconductor package of claim 1, wherein the second side of the semiconductor die is exposed through the molding material and a surface of the molding material is substantially coplanar with the second side of the semiconductor die.

3. The semiconductor package of claim 1, wherein the leadframe comprises a gate lead structure and a source lead structure.

4. The semiconductor package of claim 1, wherein the leadframe comprises a gate lead structure and a source lead structure, and the gate lead structure and the source lead structure are electrically isolated from each other.

5. The semiconductor package of claim 1, wherein the second side of the semiconductor die includes a drain region.

6. The semiconductor package of claim 1, wherein the leadframe structure comprises a layer of metal plating and a gold sublayer in the metal plating.

7. A semiconductor package comprising:

(a) a semiconductor die including a first side and a second side, wherein the semiconductor die further includes a bond pad at the first side, the bond pad comprising an uneven surface;

(b) a leadframe structure comprising (i) a substantially planar die attach region, (ii) a surface opposite the substantially planar die attach region, and (iii) a plurality of leads extending away from the die attach region;

(c) a plurality of solder structures between the semiconductor die and the leadframe structure and coupling the die attach region to the semiconductor die;

(d) a depression formed in the leadframe structure, the depression being between the one of the solder structures in the plurality of solder structures, and one of the leads in the plurality of leads, and wherein the depression is formed at an edge region of the die attach region; and

(e) a molding material covering the die attach region of the leadframe structure, the plurality of solder structures, and the first side of the semiconductor die, and also covering the surface of the leadframe structure opposite the substantially planar die attach region;

wherein the semiconductor package further comprises a plurality of depressions, the depressions in the plurality of depressions being respectively located proximate to inner portions of the leads, and

wherein the solder structures are on the die attach pad and wherein the die attach pad includes a portion that is between and bridges the solder structures.

8. The semiconductor package of claim 7, wherein the second side of the semiconductor die is exposed through the molding material.

9. The semiconductor package of claim 7, wherein the leadframe structure comprises a gate lead structure and a source lead structure.

10. The semiconductor package of claim 7, wherein the leadframe structure comprises a gate lead structure and a source lead structure, and the gate lead structure and the source lead structure are electrically isolated from each other.

11. The semiconductor package of claim 7, wherein the second side of the semiconductor die includes a drain region.

12. The semiconductor package of claim 7, wherein the leadframe structure comprises a layer of metal plating and a gold sublayer in the metal plating.