Latch or phase detector device

• US 7,123,069 B2
• Filed: 04/29/2004
• Issued: 10/17/2006
• Est. Priority Date: 04/30/2003
• Status: Expired due to Fees

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Infineon Technologies AG
• Inventors: Minzoni, Alessandro
• Primary Examiner(s): Nguyen, Linh My
• Assistant Examiner(s): Hiltunen, Thomas J.
• Application Number:
  US10/834,378
• Publication Number:
  US 20040263229A1
• Time in Patent Office: 901 Days
• Field of Search: 327/3, 327/5, 327/199, 327217-219, 327/225
• US Class Current: 327/216
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: H03D 13/003 in which both oscillations are converted by logic means into pulses which are applied to filtering or integrating means
• CPC Class Codes: H03K 3/012 Modifications of generator to improve response time or to decrease power consumption
• CPC Class Codes: H03K 3/037 Bistable circuits
• CPC Class Codes: H03K 5/26 the characteristic being duration, interval, position, frequency, or sequence

Abstract

The invention relates to a circuit device, into which a first signal and a second signal are input, wherein a first switching array is provided, by means of which it is determined which of the two signals, is the first to change its state. The circuit device may also have a second switching array, which emits an output signal, which when the first signal first has changed its state, changes its state in reaction to a change in the state of the first signal, and, when the second signal first has changed its state, changes its state in reaction to a change in the state of the first signal.

Claims

1. A circuit device, into which a first input signal and a second input signal are entered, comprising:

a first switching array to detect which of the two input signals is the first to change its state, comprising a first flip-flop which outputs first and second flip-flop output signals;

a second switching array, which emits an output signal, which, when the first input signal first changes its state, only changes its state in reaction to a change in the state of the second input signal, and, when the second input signal first changes its state, only changes its state in reaction to a change in the state of the first input signal, the second switching array comprising second and third flip-flops, and first and second NAND gates, the first NAND gate at a first input receiving the first flip-flop output signal, and the second NAND gate at a first input receiving the second flip-flop output signal, the second flip-flop outputting a third flip-flop output signal to a second input of the first NAND gate to control whether or not the first flip-flop output signal of the first flip-flop is to be relayed via the first NAND gate to the second flip-flop, and a fourth flip-flop output signal to a second input of the second NAND gate to control whether or not the second flip-flop output signal of the first flip-flop is to be relayed via the second NAND gate to the second flip-flop, the second flip-flop comprising third and fourth NAND gates with at least three inputs each.

2. The circuit device according to claim 1, in which the second input signal is a clock pulse.

3. The circuit device according to claim 1, wherein the first input signal is a data signal, which includes data to be latched by the circuit device.

4. The circuit device according to claim 1, wherein the first flip-flop is an RS flip-flop.

5. The circuit device according to claim 4, wherein the RS flip-flop has first and second NAND gates each having at least two inputs.

6. The circuit device according to claim 4, wherein the RS flip-flop has two NOR gates with at least two inputs each.

7. The circuit device according to claim 5, wherein the first input signal is fed to a first input of the first gate, and the second input signal to a first input of the second gate, and wherein the signal emitted at an output of the first gate is fed back to a second input of the second gate, and the signal emitted at an output of the second gate is fed back to a second input of the first gate.

9. The circuit device according to claim 1, wherein the second signal is fed to an input of the first gate of the second switching array.

10. The circuit device according to claim 1, wherein the second signal is fed to an input of the second gate of the second switching array.

11. The circuit device according to claim 1, which is used as a latch device.

12. The circuit device according to claim 11, wherein the data is latched in the second switching array.

13. The circuit device according to claim 12, wherein, depending on whether the first signal, or the second signal is first to change its state, the data is accordingly latched either under control of a first switching element with at least three inputs, or under control of a second switching element with at least three inputs.

14. A circuit device according to claim 13, wherein depending on which of the first signal, or the second signal is first to change its state, either the first switching element, or the second switching element is correspondingly deactivated, and the respective other switching element is activated.

15. The circuit device according to claim 14, wherein the activation and or deactivation is controlled by a control signal provided by the first switching array.

16. The circuit device according to claim 1, wherein the circuit device is used as a phase detector device.

8. A circuit device, into which a first input signal and a second input signal are entered, comprising:

a first switching array to detect which of the two input signals is the first to change its state, comprising a first flip-flop which outputs first and second flip-flop output signals;

a second switching array, which emits an output signal, which, when the first input signal first changes its state, only changes its state in reaction to a change in the state of the second input signal, and, when the second input signal first changes its state, only changes its state in reaction to a change in the state of the first input signal, the second switching array comprising second and third flip-flops, and first and second NOR gates, the first NOR gate at a first input receiving the first flip-flop output signal, and the second NOR gate at a first input receiving the second flip-flop output signal, the second flip-flop outputting a third flip-flop output signal to a second input of the first NOR gate to control whether or not the first flip-flop output signal of the first flip-flop is to be relayed via the first NOR gate to the second flip-flop, and a fourth flip-flop output signal to a second input of the second NOR gate to control whether or not the second flip-flop output signal of the first flip-flop is to be relayed via the second NOR gate to the second flip-flop, the second flip-flop comprising third and fourth NOR gates with at least three inputs each.

17. A circuit device, into which a first input signal and a second input signal are entered, comprising:

a first switching array to detect which of the two input signals is the first to change its state, comprising a first flip-flop which outputs first and second flip-flop output signals;

a second switching array, which emits an output signal, which, when the first input signal first changes its state, only changes its state in reaction to a change in the state of the second input signal, and, when the second input signal first changes its state, only changes its state in reaction to a change in the state of the first input signal, the second switching array comprising second and third flip-flops, and first and second NAND gates, the first NAND gate relaying the first flip-flop output signal of the first flip-flop to the second flip-flop in response to a third flip-flop output signal output by the second flip-flop, and the second NAND gate relaying the second flip-flop output signal of the first flip-flop to the second flip-flop in response to a fourth flip-flop output signal output by the second flip-flop, the second flip-flop comprising third and fourth NAND gates with at least three inputs each.

19. The circuit device according to claim 17, in which the second input signal is a clock pulse.

20. The circuit device according to claim 17, wherein the first input signal is a data signal, which includes data to be latched by the circuit device.

21. The circuit device according to claim 17, wherein the first flip-flop is an RS flip-flop.

22. The circuit device according to claim 21, wherein the RS flip-flop has first and second NAND gates each having at least two inputs.

23. The circuit device according to claim 21, wherein the RS flip-flop has two NOR gates with at least two inputs each.

24. The circuit device according to claim 22, wherein the first input signal is fed to a first input of the first gate, and the second input signal to a first input of the second gate, and wherein the signal emitted at an output of the first gate is fed back to a second input of the second gate, and the signal emitted at an output of the second gate is fed back to a second input of the first gate.

25. The circuit device according to claim 17, wherein the second signal is fed to an input of the first gate of the second switching array.

26. The circuit device according to claim 17, wherein the second signal is fed to an input of the second gate of the second switching array.

27. The circuit device according to claim 17, which is used as a latch device.

28. The circuit device according to claim 27, wherein the data is latched in the second switching array.

29. The circuit device according to claim 28, wherein, depending on whether the first signal, or the second signal is first to change its state, the data is accordingly latched either under control of a first switching element with at least three inputs, or under control of a second switching element with at least three inputs.

30. A circuit device according to claim 29, wherein depending on which of the first signal, or the second signal is first to change its state, either the first switching element, or the second switching element is correspondingly deactivated, and the respective other switching element is activated.

31. The circuit device according to claim 30, wherein the activation and/or deactivation is controlled by a control signal provided by the first switching array.

32. The circuit device according to claim 17, wherein the circuit device is used as a phase detector device.

18. A circuit device, into which a first input signal and a second input signal are entered, comprising:

a first switching array to detect which of the two input signals is the first to change its state, comprising a first flip-flop which outputs first and second flip-flop output signals;

a second switching array, which emits an output signal, which, when the first input signal first changes its state, only changes its state in reaction to a change in the state of the second input signal, and, when the second input signal first changes its state, only changes its state in reaction to a change in the state of the first input signal, the second switching array comprising second and third flip-flops, and first and second NOR gates, the first NOR gate relaying the first flip-flop output signal of the first flip-flop to the second flip-flop in response to a third flip-flop output signal output by the second flip-flop, and the second NOR gate relaying the second flip-flop output signal of the first flip-flop to the second flip-flop in response to a fourth flip-flop output signal output by the second flip-flop, the second flip-flop comprising third and fourth NOR gates with at least three inputs each.