Erase verify for non-volatile memory using a reference current-to-voltage converter
First Claim
1. A non-volatile memory comprising:
- an array of non-volatile memory cells arranged in columns with bit lines;
first and second comparators for comparing a bit line voltage with first and second reference voltages to respectively produce first and second output signals;
a bit line current-to-voltage converter coupled between a selected one of the bit lines and the first and second comparators to generate the bit line voltage in response to a bit line current; and
a reference current-to-voltage converter for generating the first and second reference voltages in response to a reference current, the reference current-to-voltage converter comprising;
a first resistor;
a second resistor coupled in series with the first resistor;
an activation circuit to selectively allow a current to flow through the first and second resistors; and
a reference current circuit coupled to the activation circuit for generating the current through the first and second resistors.
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Accused Products
Abstract
A memory device verify system determines a state of memory cells in a memory. The memory includes a memory array having a plurality of memory cells coupled to bit lines. A verify circuit is coupled to the bit lines to determine if memory cells have a erase level that is within predetermined upper and lower limits. The verify circuit can include first and second comparators. In one embodiment, the first comparator is used to compare a bit line current with an upper first reference current. The second comparator is used to compare a bit line current with a lower second reference current. The comparator circuit is not limited to reference currents, but can use reference voltages to compare to a bit line voltage. The verify circuit, therefore, eliminates the need for separate bit line leakage testing to identify over-erased memory cells.
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Citations
18 Claims
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1. A non-volatile memory comprising:
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an array of non-volatile memory cells arranged in columns with bit lines; first and second comparators for comparing a bit line voltage with first and second reference voltages to respectively produce first and second output signals; a bit line current-to-voltage converter coupled between a selected one of the bit lines and the first and second comparators to generate the bit line voltage in response to a bit line current; and a reference current-to-voltage converter for generating the first and second reference voltages in response to a reference current, the reference current-to-voltage converter comprising; a first resistor; a second resistor coupled in series with the first resistor; an activation circuit to selectively allow a current to flow through the first and second resistors; and a reference current circuit coupled to the activation circuit for generating the current through the first and second resistors. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A memory device comprising:
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an array of non-volatile memory cells arranged in columns using bit lines that have a bit line current indicative of a state of a memory cell; a reference current-to-voltage converter, for generating first and second reference voltages from a reference current, the reference current-to-voltage converter comprising; a first resistor; a second resistor coupled in series with the first resistor; and an activation transistor having a source coupled to the second resistor; an inverter circuit coupled between a gate of the activation transistor and a drain of the activation transistor; and a reference current circuit coupled to the drain of the activation transistor for generating a current through the first and second resistors; first and second comparators for comparing a bit line voltage with the first and second reference voltages respectively to respectively produce first and second output signals; a bit line current-to-voltage converter coupled between a selected one of the bit lines and the first and second comparators to generate the bit line voltage in response to the bit line current; and control circuitry to perform erase operations in response to the first and second output signals. - View Dependent Claims (9, 10, 11, 12)
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13. A memory system comprising:
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a processor for controlling the system; and a memory device coupled to the processor and comprising; an array of non-volatile memory cells arranged in columns using bit lines that have a bit line current indicative of a state of a memory cell; a reference current-to-voltage converter for generating first and second reference voltages from a reference current, the converter comprising; a first resistor; a second resistor coupled in series with the first resistor; an activation circuit to selectively allow a current to flow through the first and second resistors; and a reference current circuit coupled to the activation circuit for generating the current through the first and second resistors such that a first reference voltage is available between the first and second resistors and a second reference voltage is available between the second resistor and the activation circuit; a bit line current-to-voltage converter coupled between a selected one of the bit lines and the first and second comparators to generate a bit line voltage in response to the bit line current; first and second comparators for comparing the bit line voltage with the first and second reference voltages respectively to respectively produce first and second output signals; and control circuitry to perform erase operations in response to the first and second output signals. - View Dependent Claims (14, 15, 16, 17, 18)
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Specification