Erase verify for nonvolatile memory using bitline/reference current-to-voltage converters
First Claim
1. A non-volatile memory comprising:
- an array of non-volatile memory cells arranged in columns using bit lines;
first and second comparators for comparing a bit line voltage with first and second reference voltages respectively to respectively produce first and second output signals;
a bit line current-to-voltage converter coupled between a selected one of the bit lines and the first and second comparators to generate the bit line voltage in response to a bit line current; and
first and second reference current-to-voltage converters, for respectively generating the first and second reference voltages, respectively coupled between the first and second comparators and first and second reference currents, each reference current-to-voltage converter comprising;
a resistor;
an activation circuit coupled to the resistor; and
a floating gate transistor, coupled to the activation circuit, for creating a voltage drop across the resistor that provides one of the first or second reference voltages in response to the first or second reference currents respectively.
7 Assignments
0 Petitions
Accused Products
Abstract
A memory device verify system determines a state of memory cells in a memory. The memory includes a memory array having a plurality of memory cells coupled to bit lines. A verify circuit is coupled to the bit lines to determine if memory cells have a erase level that is within predetermined upper and lower limits. The verify circuit can include first and second comparators. In one embodiment, the first comparator is used to compare a bit line current with an upper first reference current. The second comparator is used to compare a bit line current with a lower second reference current. The comparator circuit is not limited to reference currents, but can use reference voltages to compare to a bit line voltage. The verify circuit, therefore, eliminates the need for separate bit line leakage testing to identify over-erased memory cells.
-
Citations
17 Claims
-
1. A non-volatile memory comprising:
-
an array of non-volatile memory cells arranged in columns using bit lines; first and second comparators for comparing a bit line voltage with first and second reference voltages respectively to respectively produce first and second output signals; a bit line current-to-voltage converter coupled between a selected one of the bit lines and the first and second comparators to generate the bit line voltage in response to a bit line current; and first and second reference current-to-voltage converters, for respectively generating the first and second reference voltages, respectively coupled between the first and second comparators and first and second reference currents, each reference current-to-voltage converter comprising; a resistor; an activation circuit coupled to the resistor; and a floating gate transistor, coupled to the activation circuit, for creating a voltage drop across the resistor that provides one of the first or second reference voltages in response to the first or second reference currents respectively. - View Dependent Claims (2, 3, 4, 5, 6, 7)
-
-
8. A memory device comprising:
-
an array of non-volatile memory cells arranged in columns using bit lines that have a bit line current indicative of a state of a memory cell; a bit line current-to-voltage converter coupled to a selected one of the bit lines for generating a bit line voltage in response to the bit line current; first and second reference current-to-voltage converters, for respectively generating first and second reference voltages from first and second reference currents, each reference current-to-voltage converter comprising; a resistor; an activation transistor having a source coupled to the resistor; an inverter circuit coupled between a gate and a drain of the activation transistor; and a floating gate transistor, coupled to the drain, for creating a voltage drop across the resistor that provides either a first or a second reference voltage in response to the first or second reference currents respectively; first and second comparators for comparing the bit line voltage with the first and second reference voltages, respectively, to respectively produce first and second output signals; and control circuitry to perform erase operations in response to the first and second output signals. - View Dependent Claims (9, 10, 11, 12)
-
-
13. A memory system comprising:
-
a processor for controlling the system; and a memory device coupled to the processor and comprising; an array of non-volatile memory cells arranged in columns using bit lines that have a bit line current indicative of a state of a memory cell; a bit line current-to-voltage converter coupled to a selected one of the bit lines for generating a bit line voltage in response to the bit line current; first and second reference current-to-voltage converters, for respectively generating first and second reference voltages from first and second reference currents, each reference current-to-voltage converter comprising; a resistor; an activation transistor having a source coupled to the resistor; an inverter circuit coupled between a gate and a drain of the activation transistor; and a floating gate transistor, coupled to the drain, for creating a voltage drop across the resistor that provides either the first or the second reference voltage in response to the first or second reference currents respectively; first and second comparators for comparing the bit line voltage with the first and second reference voltages, respectively, to respectively produce first and second output signals; and control circuitry to perform erase operations in response to the first and second output signals. - View Dependent Claims (14, 15, 16, 17)
-
Specification