Method and apparatus for achieving low power consumption during power down

• US 7,123,522 B2
• Filed: 03/10/2004
• Issued: 10/17/2006
• Est. Priority Date: 03/10/2004
• Status: Expired due to Fees

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Smith, Scott E., Ho, Duc V.
• Primary Examiner(s): LE, THONG QUOC
• Application Number:
  US10/797,240
• Publication Number:
  US 20050201178A1
• Time in Patent Office: 951 Days
• Field of Search: 365/189.11, 365/194, 365/226, 365/229, 365/191
• US Class Current: 365/189.11
• CPC Class Codes: G11C 2207/2227 Standby or low power modes
• CPC Class Codes: G11C 5/144 Detection of predetermined disconnection or reduction of power supply, e.g. power down or power standby
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence
• CPC Class Codes: G11C 7/20 Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory

Abstract

The present technique relates to a method and apparatus to provide a deep power down mode. In a memory device, such as DRAM or SRAM, various internal voltage buses provide power throughout the semiconductor chip. In a deep power down mode, grounding devices may be utilized to ground the internal voltage buses. With the internal voltage buses grounded, the outputs of the level shifters, which are control signals, may need to be forced into specific states. Through the use of the grounding devices and level shifters, leakage may be reduced and latch-up conditions may be reduced. As a result, the operation of the semiconductor chip may be enhanced because the problems associated with grounding the internal voltage buses may be diminished.

Claims

1. A system comprising:

a processor; and

a memory device coupled to the processor and comprising;

a regulator control coupled to an external voltage source; and

a plurality of internal voltage buses coupled to the regulator control to provide power to a plurality of circuits, wherein the plurality of internal voltage buses comprises an array voltage bus that provides an array voltage to array circuitry, and wherein at least one of the plurality of internal voltage buses comprises a plurality of control circuitry having at least one level shifter configured to;

receive at least one disable signal and at least one data signal;

provide a determined output signal when the at least one disable signal corresponds to a deep power down mode; and

provide an output signal that is based on the at least one data signal when the at least one disable signal does not correspond to the deep power down mode.

2. The system, as set forth in claim 1, wherein the plurality of internal voltage buses comprises an operating voltage bus that provides an operating voltage to output buffer circuitry.

3. The system, as set forth in claim 1, wherein the processor is coupled to a communication port.

4. The system, as set forth in claim 1, wherein the processor is coupled to an input device.

5. The system, as set forth in claim 1, wherein the processor is coupled to a display.

6. The system, as set forth in claim 1, wherein the control circuitry comprises at least one of an operating voltage control circuitry and a delay lock loop control circuitry.

7. The system, as set forth in claim 6, wherein the at least one level shifter in the at least one of an operating voltage control circuitry and a delay lock loop control circuitry comprises:

a first transistor coupled between a first output terminal and a low voltage source; and

a second transistor coupled between a second output terminal and the low voltage source, wherein the first and second transistors are configured to;

receive the at least one disable signal;

couple the first output terminal and the second output terminal to the low voltage source if the at least one disable signal corresponds to the deep power down mode; and

isolate the first output terminal and the second output terminal from the low voltage source if the at least one disable signal does not correspond to the deep power down mode.

8. The system, as set forth in claim 7, wherein the at least one level shifter in the at least one of an operating voltage control circuitry and the delay lock loop control circuitry comprises a third transistor coupled between the external voltage source and level shifter circuitry, wherein the third transistor is configured to:

receive the at least one disable signal;

isolate the level shifter circuitry from the external voltage source if the at least one disable signal does not correspond to the deep power down mode; and

couple the level shifter circuitry to the external voltage source if the at least one disable signal corresponds to the deep power down mode.

9. The system, as set forth in claim 1, wherein the regulator control comprises a plurality of grounding devices coupled between one of the plurality of internal voltage buses and a low voltage source, wherein each of the plurality of grounding devices is configured to:

receive the at least one disable signal;

isolate the one of the plurality of internal voltage buses from the low voltage source if the at least one disable signal does not correspond to the deep power down mode; and

couple the one of the plurality of internal voltage buses to the low voltage source if the at least one disable signal corresponds to the deep power down mode.

10. The system, as set forth in claim 9, wherein the one of the plurality of grounding devices comprises:

a transistor having a drain, a source, and a gate;

wherein the drain of the transistor is coupled between a resistor coupled to the one of the plurality of internal voltage buses and a voltage logic coupled to an external voltage source;

the source of the transistor coupled to the low voltage source; and

the gate of the transistor coupled to an input configured to receive the at least one disable signal.

11. A system comprising:

a processor; and

a memory device coupled to the processor and comprising;

a regulator control coupled to an external voltage source;

an internal voltage bus coupled to the regulator control to receive power from the regulator control; and

an output buffer circuitry coupled to the internal voltage bus and having at least one level shifter, the output buffer circuitry configured to;

receive at least one disable signal and at least one data signal, wherein the at least one data signal comprises a first disable signal and a second disable signal;

provide a predetermined output signal if the at least one disable signal corresponds to a deep power down mode, regardless of the at least one data signal; and

provide an output signal that is based on the at least one data signal if the at least one disable signal does not correspond to the deep power down mode.

12. The system, as set forth in claim 11, wherein the at least one level shifter in the output buffer circuitry comprises:

a first transistor coupled between an output terminal and an output pad voltage source, the first transistor configured to;

receive the first disable signal;

couple the output terminal to the output pad voltage source if the first disable signal corresponds to the deep power down mode; and

isolate the output terminal to the output pad voltage source if the first disable signal does not correspond to the deep power down mode.

13. The system, as set forth in claim 12, wherein the at least one level shifter in the output buffer circuitry comprises:

a second transistor coupled between the output terminal and a low output pad voltage source, and

a third transistor coupled between a gate of the second transistor and a low voltage source,

wherein the third transistor is configured to;

receive the second disable signal;

prevent the second transistor from coupling the output terminal to the low output pad voltage source if the second disable signal corresponds to the deep power down mode; and

permit the second transistor to couple the output terminal to the output pad voltage source if the second disable signal does not correspond to the deep power down mode.

14. A system comprising:

a processor; and

a memory device coupled to the processor and comprising;

a regulator control coupled to an external voltage source;

an internal voltage bus coupled to the regulator control to receive power from the regulator control; and

an output buffer circuitry coupled to the internal voltage bus and having at least one level shifter, the output buffer circuitry configured to;

receive at least one disable signal and at least one data signal, wherein the at least one data signal comprises a first disable signal, a second disable signal, and a third disable signal;

provide a predetermined output signal if the at least one disable signal corresponds to a deep power down mode, regardless of the at least one data signal; and

provide an output signal that is based on the at least one data signal if the at least one disable signal does not correspond to the deep power down mode.

15. The system, as set forth in claim 14, wherein the at least one level shifter in the output buffer circuitry comprises:

a first transistor coupled between an output terminal and a low output pad voltage source, wherein the first transistor is configured to;

receive the first disable signal;

couple the output terminal to the low output pad voltage source if the first disable signal corresponds to the deep power down mode; and

isolate the output terminal from the low output pad voltage source if the first disable signal does not correspond to the deep power down mode.

16. The system, as set forth in claim 15, wherein the at least one level shifter in the output buffer circuitry comprises:

a second transistor coupled between a gate of a third transistor and an output pad voltage source, wherein the second transistor is configured to;

receive the second disable signal;

prevent the gate of the third transistor from closing if the second disable signal corresponds to the deep power down mode; and

permit the gate of the third transistor to close if the second disable signal does not correspond to the deep power down mode.

17. The system, as set forth in claim 16, wherein the at least one level shifter in the output buffer circuitry comprises:

a fourth transistor coupled between a gate of a fifth transistor and the low output pad voltage source, wherein the fourth transistor is configured to;

receive the third disable signal;

prevent the gate of the fifth transistor from closing if the third disable signal corresponds to the deep power down mode; and

permit the gate of the fifth transistor to close if the third disable signal does not correspond to the deep power down mode.

18. A memory device comprising:

a regulator control coupled to an external voltage source;

a voltage bus coupled to the regulator control to provide power to a plurality of circuits, a control circuitry coupled to the voltage bus having a level shifter that is configured to;

receive a disable control signal and a data signal;

provide a predetermined output signal when the disable control signal corresponds to a deep power down mode;

provide an output signal that is based on the data signal when the disable control signal does not correspond to a deep power down mode,

wherein the level shifter comprises;

a first transistor coupled between a first output terminal and a low voltage source; and

a second transistor coupled between a second output terminal and the low voltage source.

19. The memory device, as set forth in claim 18, wherein the memory device comprises a dynamic random access memory (DRAM) device.

20. The memory device, as set forth in claim 18, wherein the memory device comprises a static random access memory (SRAM) device.

21. The memory device, as set forth in claim 18, wherein the regulator control comprises a grounding device configured to ground the voltage bus when a deep power down signal is received at the regulator control.

22. The memory device, as set forth in claim 18, wherein the plurality of circuits comprises output buffer circuitry.

23. The memory device, as set forth in claim 18, wherein the plurality of circuits comprises delay lock loop circuitry.

24. The memory device, as set forth in claim 18, wherein the first and second transistors are configured to:

receive the disable control signal;

couple the first output terminal and the second output terminal to the low voltage source if the disable control signal corresponds to the deep power down mode; and

isolate the first output terminal and the second output terminal from the low voltage source if the disable control signal does not correspond to the deep power down mode.

25. The memory device, as set forth in claim 24, the level shifter comprises a third transistor coupled between the external voltage source and level shifter circuitry, wherein the third transistor is configured to:

receive the disable control signal;

isolate the level shifter circuitry from the external voltage source if the disable control signal does not correspond to the deep power down mode; and

couple the level shifter circuitry to the external voltage source if the disable control signal corresponds to the deep power down mode.

26. A method of achieving low power consumption during a deep power down mode, the method comprising:

receiving an external voltage and a control signal at a regulator control;

grounding a plurality of internal voltage buses at the regulator control if the control signal indicates a deep power down mode, wherein grounding the plurality of internal voltage buses comprises closing a plurality of gates on each of a plurality of transistors to couple the plurality of internal voltage buses to ground; and

providing a plurality of voltages to the plurality of internal voltage buses from the regulator control if the control signal does not indicate the deep power down mode.

27. The method, as set forth in claim 26, comprising the act of isolating the plurality of internal voltage buses from ground if the control signal does not indicate the deep power down mode.

28. The method, as set forth in claim 26, wherein the plurality of internal voltage buses comprise at least one of an operating voltage bus, a delay lock loop voltage bus, and an array voltage bus.

29. The method, as set forth in claim 26, wherein the plurality of internal voltage buses comprise a booted power voltage bus.

30. A method of providing a deep power down mode, the method comprising:

receiving at least one disable control signal and a data signal at a level shifter;

providing a predetermined output signal when the at least one disable control signal corresponds to a deep power down mode; and

providing an output signal based on the data signal when the at least one disable control signal does not correspond to the deep power down mode.

31. The method, as set forth in claim 30, comprising:

coupling a first output terminal and a second output terminal to ground if the at least one disable control signal indicates the deep power down mode; and

isolating the first output terminal and the second output terminal from ground if the at least one disable control signal does not indicate the deep power down mode.

32. The method, as set forth in claim 31, comprising:

isolating the level shifter circuitry from an external voltage source if the at least one disable control signal does not indicate the deep power down mode; and

coupling the level shifter circuitry to the external voltage source if the at least one disable control signal indicates the deep power down mode.

33. The method, as set forth in claim 30, wherein the at least one data signal comprises a first disable signal and a second disable signal.

34. The method, as set forth in claim 33, wherein providing a predetermined output signal comprises coupling an output terminal to an output pad voltage source if the first disable signal indicates the deep power down mode;

and

wherein providing an output signal comprises isolating the output terminal from the output pad voltage source if the first disable signal does not indicate the deep power down mode.

35. The method, as set forth in claim 34, wherein providing a predetermined output signal comprises preventing the first transistor from coupling the output terminal to the low output pad voltage source if the second disable signal indicates the deep power down mode;

and

wherein providing an output signal comprises permitting the first transistor to couple the output terminal with the output pad voltage source if the second disable signal does not indicate the deep power down mode.

36. The method, as set forth in claim 30, wherein the at least one data signal comprises a first disable signal, a second disable signal, and a third disable signal.

37. The method, as set forth in claim 36, wherein providing a predetermined output signal comprises coupling an output terminal to a low output pad voltage source if the first disable signal indicates the deep power down mode;

and

wherein providing an output signal comprises isolating the output terminal from the low output pad voltage source if the first disable signal does not indicate the deep power down mode.

38. The method, as set forth in claim 37, wherein providing a predetermined output signal comprises coupling a gate of a first transistor to an output pad voltage source if the second disable signal indicates to the deep power down mode;

and

wherein providing an output signal comprises isolating the gate of the first transistor from the output pad voltage source if the second disable signal does not indicate to the deep power down mode.

39. The method, as set forth in claim 38, wherein providing a predetermined output signal comprises coupling a gate of a second transistor to the low output pad voltage source if the third disable signal indicates to the deep power down mode;

and

wherein providing an output signal comprises isolating the gate of the second transistor from the low output pad voltage source if the third disable signal does not indicate to the deep power down mode.