Low latency multi-level communication interface

• US 7,124,221 B1
• Filed: 01/06/2000
• Issued: 10/17/2006
• Est. Priority Date: 10/19/1999
• Status: Expired due to Term

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Sidiropoulos, Stefanos, Zerbe, Jared L., Werner, Carl W., Chau, Pak S., Garlepp, Bruno W., Horowitz, Mark A., Donnelly, Kevin S., Garrett, Billy W. Jr.
• Primary Examiner(s): VO, TIM T
• Application Number:
  US09/478,916
• Time in Patent Office: 2,476 Days
• Field of Search: 710/106, 327/336, 327/319, 327/333, 327/57, 327/65, 327/69, 327/70, 375/353, 348/471
• US Class Current: 710/106
• CPC Class Codes: G06F 13/1678 using bus width
• CPC Class Codes: G06F 13/4068 Electrical coupling
• CPC Class Codes: G11C 11/56 using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• CPC Class Codes: G11C 2207/108 Wide data ports
• CPC Class Codes: G11C 27/02 Sample-and-hold arrangements G11C27/04 takes precedence
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1057 Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/106 Data output latches
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1084 Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/1087 Data input latches
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 8/10 Decoders
• CPC Class Codes: H04L 25/0272 Arrangements for coupling to multiple lines, e.g. for differential transmission
• CPC Class Codes: H04L 25/0282 Provision for current-mode coupling
• CPC Class Codes: H04L 25/0296 Arrangements to ensure DC-balance
• CPC Class Codes: H04L 25/0298 Arrangement for terminating transmission lines
• CPC Class Codes: H04L 25/03006 Arrangements for removing intersymbol interference
• CPC Class Codes: H04L 25/03057 : with a recursive structure H04L25/03031 takes precedence
• CPC Class Codes: H04L 25/08 : Modifications for reducing interference; Modifications for reducing effects due to line faults ; Receiver end arrangements for detecting or overcoming line faults
• CPC Class Codes: H04L 25/4902 : Pulse width modulation; Pulse position modulation
• CPC Class Codes: H04L 25/4917 : using multilevel codes
• CPC Class Codes: H04L 7/0331 : with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock H04L7/0337 takes precedence
• CPC Class Codes: H04L 7/0332 : with an integrator-detector

Abstract

A memory system uses multiple pulse amplitude modulation (multi-PAM) output drivers and receivers to send and receive multi-PAM sigsnals. A multi-PAM signal has more than two voltage levels, with each data interval now transmitting a “symbol” at one of the valid voltage levels. In one embodiment, a symbol represents two or more bits. The multi-PAM output driver drives an output symbol onto a signal line. The output symbol represents at least two bits that include a most significant bit (MSB) and a least significant bit (LSB). The multi-PAM receiver receives the output symbol from the signal line and determines the MSB and the LSB.

Claims

1. A multi-mode pulse-amplitude-modulation (PAM) receiver for receiving a sequence of symbols, the receiver comprising:

a receiver circuit configured to receive the sequence of symbols; and

logic circuitry coupled to the receiver circuit;

wherein the multi-mode PAM receiver is capable of operating in a specified mode of a plurality of predefined modes;

wherein the received symbols are N-PAM symbols when the specified mode is a first mode, each respective N-PAM symbol in the sequence of received symbols having one of N distinct symbol values;

wherein the received symbols are M-PAM symbols when the specified mode is a second mode, each respective M-PAM symbol in the sequence of received symbols having one of M distinct symbol values; and

wherein N is not equal to M.

2. The multi-mode PAM receiver of claim 1, wherein N is equal to 2.

3. The multi-mode PAM receiver of claim 1, wherein N is equal to 2 and M is equal to 4.

4. The multi-mode PAM receiver of claim 1, wherein M and N are both integers selected from the group consisting of 2, 4, 8, and 16.

5. The multi-mode PAM receiver of claim 1, wherein the receiver circuit outputs one or more binary signals.

6. The multi-mode PAM receiver of claim 1, wherein the receiver circuit latches the sequence of symbols at a symbol rate selected from a plurality of predefined symbol rates.

7. The multi-mode PAM receiver of claim 1, wherein, when the specified mode is a second mode, the each symbol in the sequence of received symbols represents two or more bits including a most significant bit (MSB) and a least significant bit (LSB).

8. The multi-mode PAM receiver of claim 1, wherein a symbol in the sequence of received symbols represents at least a part of an address in a memory system.

9. The multi-mode PAM receiver of claim 1, wherein a symbol in the sequence of received symbols represents at least a part of a value stored in a memory system.

10. The multi-mode PAM receiver of claim 1, wherein a symbol in the sequence of received symbols represents at least a part of a command in a memory system.

11. The multi-mode PAM receiver of claim 1,

wherein, when the specified mode is a first mode, the receiver circuit receives the sequence of symbols at a first symbol rate, the sequence of symbols including one or more N-PAM modulated symbols;

wherein, when the specified mode is a second mode, the receiver circuit receives the sequence of symbols at a second symbol rate, the sequence of symbols including one or more M-PAM modulated symbols; and

wherein the first symbol rate is not equal to the second symbol rate.

12. The multi-mode PAM receiver of claim 1,

wherein the receiver circuit comprises a first receiver circuit and a second receiver circuit, each of the first and the second receiver circuits configured to output one or more signals;

wherein the signals output by the first receiver circuit represent a most significant bit (MSB) of each of the symbols in the received sequence of symbols; and

wherein, when the specified mode is a second mode, the signals output by the second receiver circuit represent a least significant bit (LSB) of each of the symbols in the received sequence of symbols.

13. The receiver of claim 1, wherein

the N-PAM symbols in the sequence of N-PAM symbols include respective symbols having all of said N distinct symbol values;

and

the M-PAM symbols in the sequence of M-PAM symbols include respective symbols having all of said M distinct symbol values.

14. The multi-mode PAM receiver of claim 5, where the receiver circuit outputs the one or more binary signals synchronized to a clock signal.

15. The multi-mode PAM receiver of claim 11, wherein the first symbol rate is twice the second symbol rate.

16. The multi-mode PAM receiver of claim 11, wherein the ratio between the second symbol rate and the first symbol rate is equal to log₂(N)/log₂(M).

17. The multi-mode PAM receiver of claim 12,

wherein the first receiver circuit includes a MSB latching comparator to compare a respective symbol in the received sequence of symbols to a first reference voltage to generate a first signal representing a state of the MSB;

wherein the second receiver circuit includes a first LSB latching comparator to compare the respective symbol to a second reference voltage and to generate a second signal representing a relationship between the respective symbol and the second reference voltage;

wherein the second receiver circuit includes a second LSB latching comparator to compare the respective symbol to a third reference voltage and to generate a third signal representing a relationship between the respective symbol and the third reference voltage; and

wherein the second receiver circuit includes logic circuitry configured to generate a fourth signal representing a state of the LSB based, at least in part, on the second signal and the third signal.

18. A multi-mode pulse-amplitude-modulation(PAM) transceiver comprising:

a multi-mode PAM output driver, configured to output a first stream of signals at a symbol rate on a first signal path; and

a multi-mode PAM receiver, configured to receive a second stream of signals at the symbol rate from a second signal path;

wherein the first stream of signals includes a sequence of N-PAM symbols when a mode signal is in a first mode signal state, each respective N-PAM symbol in the sequence of N-PAM symbols having one of N distinct symbol values;

wherein the first stream of signals includes a sequence of M-PAM symbols when the mode signal is in a second mode signal state, each respective M-PAM symbol in the sequence of M-PAM symbols having one of N distinct symbol values; and

where N is not equal to M, and wherein symbols in a respective mode in the plurality of predefined modes include two or more voltage levels.

19. The multi-mode PAM transceiver of claim 18, wherein the multi-mode PAM output driver and multi-mode PAM receiver are embodied on a single integrated circuit.

20. The multi-mode PAM transceiver of claim 18, wherein the first signal path and second signal path comprise the same physical medium.

21. The multi-mode PAM transceiver of claim 18, wherein the first stream of signals includes at least one symbol representing at least a part of an address in a memory system.

22. The multi-mode PAM transceiver of claim 18, wherein the first stream of signals includes at least one symbol representing at least a part of a value stored in a memory system.

23. The multi-mode PAM transceiver of claim 18, wherein the first stream of signals includes at least one symbol representing at least a part of a command in a memory system.

24. The multi-mode PAM transceiver of claim 18, wherein N is equal to two.

25. The multi-mode PAM transceiver of claim 18, wherein N is equal to two and M is equal to four.

26. The multi-mode PAM transceiver of claim 18, wherein M and N are both integers selected from the group consisting of 2, 4, 8, and 16.

27. The multi-mode PAM transceiver of claim 18, wherein the state of the mode signal is determined by a hardware setting.

28. The multi-mode PAM transceiver of claim 18, wherein the symbol rate is determined by control logic, and the control logic determines the state of the mode signal based, at least in part, on the second stream of signals.

29. The multi-mode PAM transceiver of claim 18, wherein the symbol rate is selected from amongst a plurality of distinct symbol rates.

30. The multi-mode PAM transceiver of claim 18, wherein the symbol rate is determined by selecting the symbol rate from amongst a plurality of symbol rates, the plurality of symbol rates including a first symbol rate and a second symbol rate, wherein the second symbol rate is twice the first symbol rate.

31. The multi-mode PAM transceiver of claim 18, wherein the symbol rate is determined by selecting the symbol rate from amongst a plurality of symbol rates, the plurality of symbol rates including a first symbol rate and a second symbol rate, wherein the ratio between the second symbol rate and the first symbol rate is equal to log₂(N)/log₂(M).

32. The multi-mode PAM transceiver of claim 18,

wherein, when a mode signal is in a first mode signal state, the first stream of signals output by the output driver is output at a first symbol rate, the first stream of signals including one or more N-PAM modulated symbols;

wherein, when a mode signal is in a second mode signal state, the second stream of signals output by the output driver is output at a second symbol rate, the second stream of signals including one or more M-PAM modulated symbols; and

wherein the first symbol rate is not equal to the second symbol rate.

33. The multi-mode PAM transceiver of claim 18,

wherein the first stream of signals has an associated first data rate when a mode signal is in a first mode signal state;

wherein the second stream of signals has an associated second data rate when the mode signal is in a second mode signal state; and

wherein the symbol rate is selected so as to make the first data rate equal to the second data rate.

34. The receiver of claim 18, wherein

the N-PAM symbols in the sequence of N-PAM symbols include respective symbols having all of said N distinct symbol values;

and

the M-PAM symbols in the sequence of M-PAM symbols include respective symbols having all of said M distinct symbol values.

35. The multi-mode PAM transceiver of claim 20, wherein the signal path is a multi-drop bus.

36. The multi-mode PAM transceiver of claim 32, wherein the first symbol rate is twice the second symbol rate.

37. The multi-mode PAM transceiver of claim 32, wherein the ratio between the second symbol rate and the first symbol rate is equal to log₂(N)/log₂(M).