Apparatus and methodology for a write hub that supports high speed and low speed data rates

• US 7,124,241 B1
• Filed: 05/07/2003
• Issued: 10/17/2006
• Est. Priority Date: 05/07/2003
• Status: Active Grant

• Current Assignee: Callahan Cellular LLC (Intellectual Ventures LLC)
• Original Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Inventors: Schober, Richard L., Colloff, Ian, Reeve, Rick, Vajjhala, Prasad
• Primary Examiner(s): Ellis, Kevin L.
• Application Number:
  US10/431,875
• Time in Patent Office: 1,259 Days
• Field of Search: 711/110
• US Class Current: 711/110
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 49/901 using storage descriptor, e.g. read or write pointers
• CPC Class Codes: H04L 49/9021 Plurality of buffers per packet
• CPC Class Codes: H04L 49/9047 including multiple buffers, e.g. buffer pools

Abstract

A write hub is described. The write hub has a plurality of registers. Each one of the registers helps generate a write address to a different memory bank from amongst a plurality of memory banks. Each of the registers are arranged in a ring so that each register can pass a pointer value toward a next register within the ring. The ring of registers further comprise a multiplexer between each of the registers. Each multiplexer has an output path that flows toward a next register within the ring relative to the multiplexer. Each multiplexer can introduce a pointer value to the ring at a next register within the ring.

Claims

1. An apparatus, comprising:

a write hub having a plurality of registers, each one of said registers to help generate a write address to a different memory bank from amongst a plurality of memory banks, each of said registers arranged in a ring so that each register can pass a pointer value toward a next register within said ring, said ring of registers further comprising a multiplexer between each of said registers, each multiplexer having an output path that flows toward a next register within said ring relative to said multiplexer, each multiplexer to introduce a pointer value to said ring at said next register within said ring.

2. The apparatus of claim 1 wherein each pointer value within said ring is either an invalid pointer value or a valid pointer value, wherein an invalid pointer prevents a write operation into the memory bank that the register holding said valid pointer value is to help generate a write address for, and wherein, a valid pointer value is a condition for a write operation into the memory bank that the register holding said valid pointer value is to help generate a write address for.

3. The apparatus of claim 2 wherein each unique valid pointer value is used as a corresponding unique write address.

4. The apparatus of claim 1 wherein said write hub further comprises a mode of operation wherein said write hub:

1) for every cycle of operation;

focuses upon a next register within said ring; and

,

2) for every N cycles of operation;

together shifts forward, by one register position within said ring, all pointer values within said ring, wherein, N is the number of registers within said ring.

5. The apparatus of claim 4 wherein, when a particular register is focused upon by said write hub, a write operation is performed into the particular memory bank that said focused upon register is to help generate a write address for if:

1) said write hub has been given access to said particular memory bank; and

2) said focused upon register is holding a valid pointer value.

6. The apparatus of claim 5 wherein whether or not said write hub has been given access to said particular memory bank is controlled by a scheduler unit.

7. The apparatus of claim 6 wherein said scheduler further comprises a second plurality of registers arranged in a ring, each one of said registers from said second plurality of registers corresponding to a different one of said memory banks and to control access to its corresponding memory bank.

8. The apparatus of claim 5 wherein, as part of said focus being placed upon said focused upon register, said write hub replaces said valid pointer value with an invalid pointer value if:

1) a packet for whom said valid pointer was devoted is finally written into said memory banks as a consequence of said write operation; and

,

2) a lead buffers worth of data has not yet been received for a next packet to be written into said memory banks.

9. The apparatus of claim 4 wherein, when a particular register is focused upon by said write hub, said write hub replaces an invalid pointer value with a fresh head pointer value within said focused upon register if:

1) said focused upon register contains an invalid pointer; and

,

2) a lead buffer'"'"'s worth of data has been received for packet for whom said fresh head pointer is devoted.

10. The apparatus of claim 9 wherein after said invalid pointer value is replaced with said fresh head pointer value within said focused upon register, a write operation is performed into the particular memory bank that said focused upon register is to help generate a write address for if said write hub has been given access to said particular memory bank.

11. The apparatus of claim 9 wherein said write hub is coupled to a pointer manager that sends said fresh head pointer value to said write hub.

12. The apparatus of claim 4 wherein, when a particular register is focused upon by said write hub, said write hub replaces the pointer value within said focused upon register with a next linked-to pointer if said pointer value within said focused upon register is exhausted, said next linked-to pointer devoted to the same packet that said exhausted pointer value was devoted to.

13. The apparatus of claim 12 wherein said register ring further comprises an incrementer between a pair of consecutive registers within said ring, said incrementer to increment a pointer value for each round trip taken through said ring, said pointer value having a plurality of lower order bits reserved for being incremented by said incrementer, said pointer value deemed exhausted when a write address has been generated with each unique combination of said lower order bits.

14. The apparatus of claim 12 wherein after said exhausted pointer value is replaced with said next linked-to pointer value within said focused upon register, a write operation is performed into the particular memory bank that said focused upon register is to help generate a write address for if said write hub has been given access to said particular memory bank.

15. The apparatus of claim 14 wherein said write hub is coupled to a pointer manager that sends said next-linked to pointer value to said write hub, said pointer manager to manage a link-list for said packet.

16. The apparatus of claim 4 wherein said mode of operation is a low speed mode of operation that can simultaneously handle N different packets that are each received from N different low speed links.

17. The apparatus of claim 16 wherein said low speed links are Infiniband 1×

links.

18. The apparatus of claim 17 wherein N=4.

19. The apparatus of claim 4 wherein said write hub further comprises a second mode of operation wherein said write hub circulates one valid pointer value within said ring, said one valid pointer value shifted forward to a next register within said ring for each cycle of operation to cause one write address to be generated per cycle of operation, each write address targeted at the particular memory bank that said next register holding said valid pointer value is to help generate a write address for.

20. The apparatus of claim 19 wherein said write hub replaces, within said ring, said one valid pointer value with a fresh head pointer value if:

1) said one valid pointer has completed a round trip through said ring; and

,

2) enough of a next packet has been received to commence writing said next packet into said memory banks; and

3) a packet for whom said one valid pointer was devoted is completely written into said memory banks.

21. The apparatus of claim 19 wherein said write hub increments said one valid pointer and circulates said incremented pointer value through said ring if:

1) said one valid pointer value has completed a round trip through said ring; and

,

2) said one valid pointer value is not yet deemed an exhausted pointer value; and

,

3) a packet for whom said one valid pointer value was devoted is not completely written into said memory banks.

22. The apparatus of claim 19 wherein said write hub replaces, within said ring, said one valid pointer value with a next linked to pointer value if:

1) said one valid pointer value has completed a round trip through said ring; and

,

2) said one valid pointer value is deemed an exhausted pointer value; and

,

3) a packet for whom said one valid pointer value was devoted is not completely written into said memory banks.

23. The apparatus of claim 19 wherein said write hub replaces, within said ring, said one valid pointer value with an invalid pointer value if:

1) said one valid pointer has completed a round trip through said ring; and

,

2) enough of a next packet has not yet been received to commence writing said next packet into said memory banks; and

3) a packet for whom said one valid pointer was devoted is completely written into said memory banks.

24. The apparatus of claim 19 wherein said second mode of operation is a high speed mode of operation that can handle one packet received from one high speed link.

25. The apparatus of claim 24 wherein said high speed link is an Infiniband high speed link.

26. The apparatus of claim 25 wherein said high speed link is a 4×

Infiniband high speed link.

27. The apparatus of claim 1 wherein said write hub is part of an input port that writes packets received from one or more links into said memory banks, said input port further comprising a request manager that:

1) generates a request data structure for each of said packets; and

,

2) sends each request data structure to an arbiter unit, said arbiter unit to decide when each packet is to be read from said memory banks so that it can be forwarded to a switch core.

28. The apparatus of claim 27 wherein said request data structure further comprises:

1) a head pointer value for its corresponding packet; and

2) an indication as to which memory bank amongst said plurality of memory banks that a first piece of said corresponding packet was written into.

29. The apparatus of claim 28 wherein said request data structure further comprises;

1) the size of said corresponding packet; and

2) the destination address of said corresponding packet.

30. The apparatus of claim 27 wherein said input port further comprises a scheduler to scheduler reading and writing activity across said memory banks, said scheduler having an input where a grant is received from said arbiter for each of said packets.

35. The apparatus of claim 30 wherein, within said first mode of operation, as part of said focus being placed upon said focused upon register, said write hub replaces said valid pointer value with an invalid pointer value if:

1) a packet for whom said valid pointer value was devoted is finally written into said memory banks as a consequence of a write operation being performed commensurate with said generation of said write address; and

,

2) a lead buffer'"'"'s worth of data has not yet been received for a next packet to be written into said memory banks.

36. The apparatus of claim 30 wherein, within said first mode of operation, when a particular register is focused upon by said write hub, said write hub replaces an invalid pointer value with a fresh head pointer value within said focused upon register if:

1) said focused upon register contains an invalid pointer, and,

2) a lead buffer'"'"'s worth of data has been received for packet for whom said fresh head pointer is devoted.

37. The apparatus of claim 36 wherein after said invalid pointer value is replaced with said fresh head pointer value within said focused upon register, a write operation is performed into the particular memory bank that said focused upon register is to help generate a write address for if said write hub has been given access to said particular memory bank.

38. The apparatus of claim 36 wherein said write hub is coupled to a pointer manager that sends said fresh head pointer value to said write hub.

39. The apparatus of claim 30 wherein, within said first mode of operation, when a particular register is focused upon by said write hub, said write hub replaces the pointer value within said focused upon register with a next linked-to pointer if said pointer value within said focused upon register is exhausted, said next linked to pointer devoted to the same packet that said exhausted pointer value was devoted to.

40. The apparatus of claim 39 wherein said register ring further comprises an incrementer between a pair of consecutive registers within said ring, said incrementer to increment a pointer value for each round trip taken through said ring, said pointer value having a plurality of lower order bits reserved for being incremented by said incrementer, said pointer value deemed exhausted when a write address has been generated with each unique combination of said lower order bits.

41. The apparatus of claim 39 wherein after said exhausted pointer value is replaced with said next linked-to pointer value within said focused upon register, a write operation is performed into the particular memory bank that said focused upon register is to help generate a write address for if said write hub has been given access to said particular memory bank.

42. The apparatus of claim 41 wherein said write hub is coupled to a pointer manager that sends said next-linked to pointer value to said write hub, said pointer manager to manage a link-list for said packet.

43. The apparatus of claim 30 wherein, within said second mode of operation, said write hub replaces, within said ring, said one valid pointer value with a fresh head pointer value if:

1) said one valid pointer has completed a round trip through said ring; and

,

2) enough of a next packet has been received to commence writing said next packet into said memory banks; and

3) a packet for whom said one valid pointer was devoted is completely written into said memory banks.

44. The apparatus of claim 30 wherein, within said second mode of operation, said write hub increments said one valid pointer and circulates said incremented pointer value through said ring if:

1) said one valid pointer value has completed a roundtrip through said ring; and

,

2) said one valid pointer value is not yet deemed an exhausted pointer value; and

,

3) a packet for whom said one valid pointer value was devoted is not completely written into said memory banks.

45. The apparatus of claim 30 wherein, within said second mode of operation, said write hub replaces, within said ring, said one valid pointer value with a next linked to pointer value if:

1) said one valid pointer value has completed a roundtrip through said ring; and

,

2) said one valid pointer value is deemed an exhausted pointer value; and

,

3) a packet for whom said one valid pointer value was devoted is not completely written into said memory banks.

46. The apparatus of claim 30 wherein, within said second mode of operation, said write hub replaces, within said ring, said one valid pointer value with an invalid pointer value if:

1) said one valid pointer has completed a round trip through said ring; and

,

2) enough of a next packet has not yet been received to commence writing said next packet into said memory banks; and

3) a packet for whom said one valid pointer was devoted is completely written into said memory banks.

47. The apparatus of claim 30 wherein said first mode of operation is a low speed mode of operation that can simultaneously handle N different packets that are each received from N different low speed links.

48. The apparatus of claim 47 wherein said low speed links are Infiniband 1×

links.

49. The apparatus of claim 48 wherein N=4.

50. The apparatus of claim 30 wherein said second mode of operation is a high speed mode of operation that can handle one packet received from one high speed link.

51. The apparatus of claim 50 wherein said high speed link is an Infiniband high speed link.

52. The apparatus of claim 51 wherein said high speed link is a 4×

Infiniband high speed link.

53. The apparatus of claim 30 wherein said write hub is part of an input port that writes packets received from one or more links into said memory banks, said input port further comprising a request manager that:

1) generates a request data structure for each of said packets; and

,

2) sends each request data structure to an arbiter unit, said arbiter unit to decide when each packet is to be read from said memory banks so that it can be forwarded to a switch core.

54. The apparatus of claim 53 wherein said request data structure further comprises:

1) a head pointer value for its corresponding packet; and

2) an indication as to which memory bank amongst said plurality of memory banks that a first piece of said corresponding packet was written into.

55. The apparatus of claim 54 wherein said request data structure further comprises;

1) the size of said corresponding packet; and

2) the destination address of said corresponding packet.

56. The apparatus of claim 53 wherein said input port further comprises a scheduler to scheduler reading and writing activity across said memory banks, said scheduler having an input where a grant is received from said arbiter for each of said packets.

31. An apparatus, comprising:

a write hub having a plurality of registers, each one of said registers to help generate a write address to a different memory bank from amongst a plurality of memory banks, each of said registers arranged in a ring so that each register can pass a pointer value toward a next register within said ring, said ring of registers further comprising a multiplexer between each of said registers, each multiplexer having an output path that flows toward a next register within said ring relative to said multiplexer, each multiplexer to introduce a pointer value to said ring at said next register within said ring, said write hub having a first mode of operation and a second mode of operation wherein;

in said first mode of operation said write hub;

1) for every cycle of operation;

focuses upon a next register within said ring to cause a write address to be generated for the particular memory bank that said focused upon register is to help generate a write address for if;

a) said write hub has been given access to said particular memory bank and

b) said focused upon register is holding a valid pointer value;

2) for every N cycles of operation;

together shifts forward, by one register position within said ring, all pointer values within said ring, wherein, N is the number of registers within said ring;

in said second mode of operation said write hub;

circulates one valid pointer value within said ring, said one valid pointer value shifted forward to a next register within said ring for each cycle of operation to cause one write address to be generated per cycle of operation for a packet for whom said one valid pointer value is devoted, each write address targeted at the particular memory bank that said next register holding said valid pointer value is to help generate a write address for.

32. The apparatus of claim 31 wherein each unique valid pointer value is used as corresponding unique write address.

33. The apparatus of claim 31 wherein, within said first mode of operation, whether or not said write hub has been given access to said particular memory bank is controlled by a scheduler unit.

34. The apparatus of claim 33 wherein said scheduler unit further comprises a second plurality of registers arranged in a ring, each one of said registers from said second plurality of registers corresponding to a different one of said memory banks and to control access to its corresponding memory bank.

57. A method, comprising:

for every cycle of operation;

at a next register within a ring of registers, each one of said registers to help generate a write address to a different memory bank from amongst a plurality of memory banks, causing a write address to be generated for the particular memory bank that said next register is to help generate a write address for if;

a) access has been given to said particular memory bank and

b) said next register is holding a valid pointer value; and

for every N cycles of operation;

together shifting forward, by one register position within said ring, all pointer values within said ring, wherein, N is the number of registers within said ring.

58. The method of claim 57 wherein each unique valid pointer value is used as a corresponding unique write address.

59. The method of claim 57 further comprising circulating values within a second ring of registers to control access to said particular memory bank, one of said values to specify which one of said memory banks can be written to.

60. The method of claim 57 further comprising, as a consequence of a write operation being performed that finishes the writing of a packet into said memory banks wherein said writing of said packet is commensurate with said write address being generated, replacing said valid pointer value with an invalid pointer value within said next register if an amount of data from a next packet to be written into said memory banks has not yet been received in a sufficient quantity to start writing said next packet into said memory banks.

61. The method of claim 57 further comprising, if said next register contains an invalid pointer value, replacing said invalid pointer value with a fresh head pointer value if an amount of data from a packet for whom said fresh head pointer is devoted has been received in a sufficient quantity to start writing said packet into said memory banks.

62. The method of claim 61 further comprising, if access has been given to the particular memory bank that said next register is to help generate a write address for, generating a write address with said fresh head pointer after said invalid pointer value is replaced with said fresh head pointer value, said write address being part of a write operation that writes a lead buffer'"'"'s worth of data from said packet into said particular memory bank.

63. The method of claim 61 further comprising receiving said fresh head pointer value from a pointer manager prior to its placement into said next register.

64. The method of claim 57 further comprising replacing, within said focused upon register, said valid pointer value with a next linked-to pointer value if said valid pointer value within said next register is exhausted, said next linked-to pointer value devoted to the same packet that said exhausted pointer value was devoted to.

65. The method of claim 57 further comprising incrementing a pointer value for each round trip taken through said ring, said pointer value having a plurality of lower order bits reserved for being incremented, each pointer value deemed exhausted when a write address has been generated with each unique combination of said lower order bits.

66. The method of claim 65 further comprising after said exhausted pointer value is replaced with said next linked-to pointer value within said next register, if access has been given to said particular memory bank that said next register is to help generate a write address for, performing a write operation into said particular memory bank that said next register is to help generate a write address for.

67. The method of claim 66 further comprising receiving said next-linked to pointer value from a pointer manager that manages a link-list for said packet.

68. The apparatus of claim 57 further comprising handling N different packets that are each received from N different low speed links.

69. The apparatus of claim 68 wherein said low speed links are Infiniband 1×

links.

70. The apparatus of claim 69 wherein N=4.

71. The method of claim 57 further comprising:

changing a mode of operation to perform a second method, said second method comprising;

circulating one valid pointer value within said ring, said one valid pointer value shifted forward to a next register within said ring for each cycle of operation to cause one write address to be generated per cycle of operation for a packet for whom said one valid pointer value is devoted, each write address targeted at the particular memory bank that said next register holding said valid pointer value is to help generate a write address for.

72. The method of claim 71 wherein said second method can handle one packet received from one high speed link.

73. The method of claim 72 wherein said high speed link is an Infiniband high speed link.

74. The method of claim 73 wherein said high speed link is a 4×

Infiniband high speed link.

75. The method of claim 71 wherein said second method further comprises:

replacing, within said ring, said one valid pointer value with a fresh head pointer value if;

1) said one valid pointer has completed a round trip-through said ring; and

,

2) enough of a next packet has been received to commence writing said next packet into said memory banks; and

3) a packet for whom said one valid pointer was devoted is completely written into said memory banks.

76. The method of claim 71 wherein said second method further comprises:

incrementing said one valid pointer and circulating said incremented pointer value through said ring if;

1) said one valid pointer value has completed a round trip through said ring; and

,

2) said one valid pointer value is not yet deemed an exhausted pointer value; and

,

3) a packet for whom said one valid pointer value was devoted is not completely written into said memory banks.

77. The method of claim 71 wherein said second method further comprises:

replacing, within said ring, said one valid pointer value with a next linked to pointer value if;

1) said one valid pointer value has completed a round trip through said ring; and

,

2) said one valid pointer value is deemed an exhausted pointer value; and

,

3) a packet for whom said one valid pointer value was devoted is not completely written into said memory banks.

78. The method of claim 71 wherein said second method further comprises:

replacing, within said ring, said one valid pointer value with an invalid pointer value if;

1) said one valid pointer has completed a round trip through said ring; and

,

2) enough of a next packet has not yet been received to commence writing said next packet into said memory banks; and

3) a packet for whom said one valid pointer was devoted is completely written into said memory banks.

79. The method of claim 57 further comprising:

1) generating a request data structure for a packet to be written into said memory banks; and

,

2) sending said request data structure to an arbiter unit, said arbiter unit to decide when said packet is to be read from said memory banks so that it can be forwarded to a switch core.

80. The method of claim 79 wherein said request data structure further comprises:

1) a head pointer value for its corresponding packet; and

2) an indication as to which memory bank amongst said plurality of memory banks that a first piece of said packet was written into.

81. The method of claim 79 wherein said request data structure further comprises;

1) the size of said packet; and

2) the destination address of said packet.

82. A machine readable medium having stored thereon a computer program and a description of a circuit, the computer program comprising executable instructions that when executed by a processor direct the processor to emulate the operation of the circuit, said operation comprising:

using a write hub having a plurality of registers, each one of said registers configured to help generate a write address to a different memory bank from amongst a plurality of memory banks, each of said registers arranged in a ring;

passing a pointer value toward a next register within said ring, said ring of registers further comprising a multiplexer between each of said registers, each multiplexer having an output path that flows toward a next register within said ring relative to said multiplexer, each multiplexer configured to introduce a pointer value to said ring at said next register within said ring; and

causing a write address to be generated for the particular memory bank that said next register is to help generate a write address for if;

a) access has been given to said particular memory bank and

b) said next register is holding a valid pointer value; and

for every N cycles of operation;

together shifting forward, by one register position within said ring, all pointer values within said ring, wherein, N is the number of registers within said ring.

83. The machine readable medium of claim 82 wherein said description is within a VHDL format.

84. The machine readable medium of claim 82 wherein said description is within a Verilog format.

85. The machine readable medium of claim 82 where said description is a gate level netlist.