Methods and apparatus for indexed register access

• US 7,124,259 B2
• Filed: 05/03/2004
• Issued: 10/17/2006
• Est. Priority Date: 05/03/2004
• Status: Expired due to Fees

• Current Assignee: Sony Computer Entertainment Incorporated (Sony Group Corp.)
• Original Assignee: Sony Computer Entertainment Incorporated (Sony Group Corp.)
• Inventors: Iwamoto, Tatsuya, Yasue, Masahiro
• Primary Examiner(s): Ellis, Kevin L.
• Application Number:
  US10/838,051
• Publication Number:
  US 20050251659A1
• Time in Patent Office: 897 Days
• Field of Search: 711/154, 711/215
• US Class Current: 711/154
• CPC Class Codes: G06F 9/30032 Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06F 9/30043 LOAD or STORE instructions; Clear instruction
• CPC Class Codes: G06F 9/30134 Register stacks; shift registers
• CPC Class Codes: G06F 9/35 Indirect addressing
• CPC Class Codes: G06F 9/355 Indexed addressing

Abstract

Methods and apparatus enable the execution of processing sequences including the computation of a register index that is loaded into one of a plurality of registers, utilizing that index to identify another of the plurality of registers, and accessing data from or copying data to the indexed register to or from yet another register or a memory location.

Claims

1. A method, comprising:

performing computations to obtain a calculated value;

loading the calculated value into at least one of a plurality of hardware registers of a processing system, each hardware register having an identifier number associated therewith;

using the calculated value as an index to one of the identifier numbers and the hardware register associated therewith; and

accessing data from the hardware register indexed by the calculated value.

2. The method of claim 1, further comprising:

copying the data into another one of the hardware registers.

3. The method of claim 2, wherein the step of copying the data into another one of the hardware registers occurs without requiring access into a random access memory of the processing system.

4. The method of claim 1, wherein the computations are performed while the processing system is executing a software program.

5. The method of claim 1, wherein the steps are used in a table look up procedure that does not require access into a random access memory of the processing system.

6. The method of claim 1, further comprising:

accessing the calculated value from the at least one hardware register and using the calculated value as a pointer to the indexed hardware register.

7. The method of claim 2, wherein the steps are executed in response to a computer instruction defining a data move from a source hardware register to a destination hardware register.

8. The method of claim 7, wherein the source hardware register is the hardware register indexed by the calculated value, and the destination hardware register is the other hardware register.

9. The method of claim 8, wherein the computer instruction may be characterized by the following operational code:

mov*Rm, Rp

wherein Rm is a hardware register in which the calculated value is located, and Rp is the destination register.

10. The method of claim 1, wherein processing system includes a reduced instruction set computer (RISC) microprocessor.

11. A storage medium containing at least one software instruction operable to cause a processor and a plurality of hardware registers, each hardware register having an identifier number associated therewith, to perform steps, comprising:

performing computations to obtain a calculated value;

loading the calculated value into at least one of a the plurality of hardware registers;

using the calculated value as an index to one of the identifier numbers and the hardware register associated therewith; and

accessing data from the hardware register indexed by the calculated value.

12. The storage medium of claim 11, wherein the steps further comprise:

copying the data into another one of the hardware registers.

13. The storage medium of claim 11, wherein the step of copying the data into another one of the hardware registers occurs without requiring access into a random access memory coupled to the processor.

14. The storage medium of claim 11, wherein the computations are performed during the execution of a software program containing the at least one software instruction.

15. The storage medium of claim 11, wherein the steps are used in a table look up procedure that does not require access into a random access memory coupled to the processor.

16. The storage medium of claim 11, further comprising:

accessing the calculated value from the at least one hardware register and using the calculated value as a pointer to the indexed hardware register.

17. The storage medium of claim 13, wherein the at least one software instruction defines a data move from a source hardware register to a destination hardware register.

18. The storage medium of claim 17, wherein the source hardware register is the hardware register indexed by the calculated value, and the destination hardware register is the other hardware register.

19. The storage medium of claim 18, wherein the at least one software instruction may be characterized by the following operational code:

mov*Rm, Rp

wherein Rm is a hardware register in which the calculated value is located, and Rp is the destination register.

20. The storage medium of claim 11, wherein processor includes a reduced instruction set computer (RISC) microprocessor.

21. A processing system including a storage medium containing at least one software instruction operable to cause a processor and a plurality of hardware registers of the processing system, each hardware register having an identifier number associated therewith, to perform steps, comprising:

performing computations to obtain a calculated value;

loading the calculated value into at least one of a the plurality of hardware registers;

using the calculated value as an index to one of the identifier numbers and the hardware register associated therewith; and

accessing data from the hardware register indexed by the calculated value.

22. The processing system of claim 21, wherein the steps further comprise:

copying the data into another one of the hardware registers.

23. The processing system of claim 21, wherein the step of copying the data into another one of the hardware registers occurs without requiring access into a random access memory coupled to the processor.

24. The processing system of claim 21, wherein the computations are performed during execution of a software program containing the at least one software instruction.

25. The processing system of claim 21, wherein the steps are used in a table look up procedure that does not require access into a random access memory coupled to the processor.

26. The processing system of claim 21, further comprising:

accessing the calculated value from the at least one hardware register and using the calculated value as a pointer to the indexed hardware register.

27. The processing system of claim 22, wherein the at least one software instruction defines a data move from a source hardware register to a destination hardware register.

28. The processing system of claim 27, wherein the source hardware register is the hardware register indexed by the calculated value, and the destination hardware register is the other hardware register.

29. The processing system of claim 28, wherein the at least one software instruction may be characterized by the following operational code:

mov*Rm, Rp

wherein Rm is a hardware register in which the calculated value is located, and Rp is the destination register.

30. The processing system of claim 21, wherein processor includes a reduced instruction set computer (RISC) microprocessor.

31. A method, comprising:

performing computations to obtain a calculated value;

loading the calculated value into at least one of a plurality of hardware registers of a processing system, each hardware register having an identifier number associated therewith;

using the calculated value as an index to one of the identifier numbers and the hardware register associated therewith; and

accessing data from another one of the hardware registers.

32. The method of claim 31, further comprising:

copying the data into the hardware register indexed by the calculated value.

33. The method of claim 31, wherein the step of copying the data into the hardware register indexed by the calculated value occurs without requiring access into a random access memory of the processing system.

34. The method of claim 31, wherein the computations are performed during execution of a software program running on the processing system.

35. The method of claim 31, wherein the steps are used in a table look up procedure that does not require access into a random access memory of the processing system.

36. The method of claim 31, further comprising:

accessing the calculated value from the at least one hardware register and using the calculated value as a pointer to the indexed hardware register.

37. The method of claim 32, wherein the steps are executed in response to a computer instruction defining a data move from a source hardware register to a destination hardware register.

38. The method of claim 37, wherein the source hardware register is the other hardware register, and the destination hardware register is the hardware register indexed by the calculated value.

39. The method of claim 38, wherein the computer instruction may be characterized by the following operational code:

mov Rp,*Rm

wherein Rm is a hardware register in which the calculated value is located, and Rp is the source register.

40. The method of claim 31, wherein processing system includes a reduced instruction set computer (RISC) microprocessor.

41. A storage medium containing at least one software instruction operable to cause a processor and a plurality of hardware registers, each hardware register having an identifier number associated therewith, to perform steps, comprising:

performing computations to obtain a calculated value;

loading the calculated value into at least one of the plurality of hardware registers;

using the calculated value as an index to one of the identifier numbers and the hardware register associated therewith; and

accessing data from another one of the hardware registers.

42. The storage medium of claim 41, wherein the steps further comprise:

copying the data into the hardware register indexed by the calculated value.

43. The storage medium of claim 41, wherein the step of copying the data into the hardware register indexed by the calculated value occurs without requiring access into a random access memory coupled to the processor.

44. The storage medium of claim 41, wherein the computations are performed during execution of a software program containing the at least one software instruction.

45. The storage medium of claim 41, wherein the steps are used in a table look up procedure that does not require access into a random access memory coupled to the processor.

46. The storage medium of claim 41, further comprising:

accessing the calculated value from the at least one hardware register and using the calculated value as a pointer to the indexed hardware register.

47. The storage medium of claim 42, wherein the software instruction defines a data move from a source hardware register to a destination hardware register.

48. The storage medium of claim 47, wherein the source hardware register is the other hardware register, and the destination hardware register is the hardware register indexed by the calculated value.

49. The storage medium of claim 48, wherein the at least one software instruction may be characterized by the following operational code:

mov Rp,*Rm

wherein Rm is a hardware register in which the calculated value is located, and Rp is the source register.

50. The storage medium of claim 41, wherein processor is a reduced instruction set computer (RISC) microprocessor.

51. A processing system including a storage medium containing at least one software instruction operable to cause a processor and a plurality of hardware registers of the processing system, each hardware register having an identifier number associated therewith, to perform steps, comprising:

performing computations to obtain a calculated value;

loading the calculated value into at least one of the plurality of hardware registers;

using the calculated value as an index to one of the identifier numbers and the hardware register associated therewith; and

accessing data from another one of the hardware register.

52. The processing system of claim 51, wherein the steps further comprise:

copying the data into the hardware register indexed by the calculated value.

53. The processing system of claim 51, wherein the step of copying the data into the hardware register indexed by the calculated value occurs without requiring access into a random access memory coupled to the processor.

54. The processing system of claim 51, wherein the computations are performed during execution of a software program containing the at least one software instruction.

55. The processing system of claim 51, wherein the steps are used in a table look up procedure that does not require access into a random access memory coupled to the processor.

56. The processing system of claim 51, further comprising:

accessing the calculated value from the at least one hardware register and using the calculated value as a pointer to the indexed hardware register.

57. The processing system of claim 52, wherein the software instruction defines a data move from a source hardware register to a destination hardware register.

58. The processing system of claim 57, wherein the source hardware register is the other hardware register, and the destination hardware register is the hardware register indexed by the calculated value.

59. The processing system of claim 58, wherein the at least one software instruction may be characterized by the following operational code:

mov Rp,*Rm

wherein Rm is a hardware register in which the calculated value is located, and Rp is the source register.

60. The processing system of claim 51, wherein processor is a reduced instruction set computer (RISC) microprocessor.

61. A method, comprising:

performing computations to obtain a calculated value;

loading the calculated value into at least one of a plurality of hardware registers of a processing system, each hardware register having an identifier number associated therewith;

using the calculated value as an index to one of the identifier numbers and the hardware register associated therewith; and

at least one of (i) storing data into a random access memory (RAM) coupled to the processor by accessing data from the hardware register indexed by the calculated value and copying the data into the RAM at a specified address; and

(ii) loading data from the RAM by accessing data from the RAM at a specified address and copying the data into the hardware register indexed by the calculated value.

62. A storage medium containing at least one software instruction operable to cause a processor and a plurality of hardware registers, each hardware register having an identifier number associated therewith, to perform steps, comprising:

performing computations to obtain a calculated value;

loading the calculated value into at least one of the hardware registers;

using the calculated value as an index to one of the identifier numbers and the hardware register associated therewith; and

at least one of (i) storing data into a random access memory (RAM) coupled to the processor by accessing data from the hardware register indexed by the calculated value and copying the data into the RAM at a specified address; and

(ii) loading data from the RAM by accessing data from the RAM at a specified address and copying the data into the hardware register indexed by the calculated value.

63. A processing system including a storage medium containing at least one software instruction operable to cause a processor and a plurality of hardware registers of the processing system, each hardware register having an identifier number associated therewith, to perform steps, comprising:

performing computations to obtain a calculated value;

loading the calculated value into at least one of the hardware registers;

using the calculated value as an index to one of the identifier numbers and the hardware register associated therewith; and

at least one of (i) storing data into a random access memory (RAM) coupled to the processor by accessing data from the hardware register indexed by the calculated value and copying the data into the RAM at a specified address; and

(ii) loading data from the RAM by accessing data from the RAM at a specified address and copying the data into the hardware register indexed by the calculated value.