Capacitor layout technique for reduction of fixed pattern noise in a CMOS sensor

• US 7,124,384 B2
• Filed: 07/01/2004
• Issued: 10/17/2006
• Est. Priority Date: 08/13/2002
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Rossi, Giuseppe
• Primary Examiner(s): Lin, Sun James
• Application Number:
  US10/881,002
• Publication Number:
  US 20050003624A1
• Time in Patent Office: 838 Days
• Field of Search: 716/8, 716/9, 716/1, 257/535
• US Class Current: 716/119
• CPC Class Codes: H01L 27/0805 Capacitors only
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 29/94 Metal-insulator-semiconductors, e.g. MOS
• CPC Class Codes: Y10S 438/957 Making metal-insulator-metal device

Abstract

A new capacitor architecture includes a front plate of the capacitor formed form a first polysilicon layer. The front plate is surround by a first dielectric layer and a second dielectric layer. The back plate of the capacitor is formed from one layer of a first two-layer conductive structure which surrounds the first dielectric layer and the second dielectric layer. The two-layer conductive structure is an equal potential structure and includes a conductive coupling between the two layers.

Claims

1. A capacitor, comprising:

a first plate;

a second plate;

a first shield, said first shield comprising a first surface and a second surface, said first surface and said second surface being equal potential surfaces; and

a second shield, said second shield comprising a third surface and a fourth surface, said third surface and said fourth surface being equal potential surfaces;

wherein

said first plate and said second plate are disposed to form two plates of said capacitor,

said first surface and said second surface are disposed to shield said first plate,

and said third surface and said fourth surface are disposed to shield said first plate and said second plate.

2. The capacitor of claim 1, wherein said second shield is disposed to also shield said first shield.

3. The capacitor of claim 1, wherein said capacitor is formed over a substrate.

4. The capacitor of claim 3, wherein one of said first surface and said second surface is a polysilicon layer formed over said substrate.

5. The capacitor of claim 3, wherein one of said first surface and said second surface is a metal layer formed over said substrate.

6. The capacitor of claim 3, wherein one of said third surface and said fourth surface is said substrate formed over said substrate.

7. The capacitor of claim 3, wherein one of said third surface and said fourth surface is a metal layer formed over said substrate.

8. The capacitor of claim 3, wherein one of said first plate and said second plate is a metal layer formed over said substrate.

9. The capacitor of claim 3, wherein one of said first plate and said second plate is a polysilicon layer formed over said substrate.

10. A circuit for sampling signals produced by a pixel, comprising:

an input line for receiving signals produced by said pixel;

a sample capacitor; and

a switch for controllably coupling said sample capacitor to said input line;

wherein said sample capacitor is fabricated as a semiconductor device and further comprises;

a first plate;

a second plate;

a first shield, said first shield comprising a first surface and a second surface, said first surface and said second surface being equal potential surfaces; and

a second shield, said second shield comprising a third surface and a fourth surface, said third surface and said fourth surface being equal potential surfaces;

wherein

said first plate and said second plate are disposed to form two plates of said sample capacitor,

said first surface and said second surface are disposed to shield said first plate,

and said third surface and said fourth surface are disposed to shield said first plate and said second plate.

11. The circuit of claim 10, wherein said second shield is disposed to also shield said first shield.

12. The circuit of claim 10, wherein said sample capacitor is formed over a substrate.

13. The circuit of claim 12, wherein one of said first surface and said second surface is a polysilicon layer formed over said substrate.

14. The circuit of claim 12, wherein one of said first surface and said second surface is a metal layer formed over said substrate.

15. The circuit of claim 12, wherein one of said third surface and said fourth surface is said substrate formed over said substrate.

16. The circuit of claim 12, wherein one of said third surface and said fourth surface is a metal layer formed over said substrate.

17. The circuit of claim 12, wherein one of said first plate and said second plate is a metal layer formed over said substrate.

18. The circuit of claim 12, wherein one of said first plate and said second plate is a polysilicon layer formed over said substrate.