Interconnected high speed electron tunneling devices

• US 7,126,151 B2
• Filed: 01/06/2003
• Issued: 10/24/2006
• Est. Priority Date: 05/21/2001
• Status: Expired due to Term

• Current Assignee: The Board of Regents of the University of Colorado (University of Colorado System)
• Original Assignee: The Board of Regents of the University of Colorado (University of Colorado System)
• Inventors: Estes, Michael J., Moddel, Garret
• Primary Examiner(s): Nuynh, Andy
• Assistant Examiner(s): Nguyen, Thinh T
• Application Number:
  US10/337,427
• Publication Number:
  US 20030133339A1
• Time in Patent Office: 1,387 Days
• Field of Search: 257/25, 257/30, 257/31, 257/36, 257/37
• US Class Current: 257/25
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: B82Y 20/00 Nanooptics, e.g. quantum optics or photonic crystals
• CPC Class Codes: G02B 2006/12123 Diode
• CPC Class Codes: G02B 2006/1213 comprising photonic band-gap structures or photonic lattices
• CPC Class Codes: G02B 2006/12142 Modulator
• CPC Class Codes: G02B 6/12004 Combinations of two or more optical elements
• CPC Class Codes: G02B 6/1226 involving surface plasmon interaction
• CPC Class Codes: G02B 6/34 utilising prism or grating G02B6/293 takes precedence
• CPC Class Codes: G02B 6/4201 Packages, e.g. shape, construction, internal or external details
• CPC Class Codes: G02B 6/4279 Radio frequency signal propagation aspects of the electrical connection, high frequency adaptations
• CPC Class Codes: G02B 6/4292 the light guide being disconnectable from the opto-electronic element, e.g. mutually self aligning arrangements
• CPC Class Codes: G02B 6/43 Arrangements comprising a plurality of opto-electronic elements and associated optical interconnections
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06534 Optical coupling
• CPC Class Codes: H01L 23/48 Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H01L 31/035236 Superlattices; Multiple quantum well structures
• CPC Class Codes: H01L 31/06 : characterised by potential barriers
• CPC Class Codes: H01L 31/101 : Devices sensitive to infrared, visible or ultraviolet radiation
• CPC Class Codes: H10N 70/00 : Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching integrated devices or assemblies of multiple devices H10N79/00
• CPC Class Codes: Y02E 10/50 : Photovoltaic [PV] energy

Abstract

An integrated circuit chip includes a formation of integrated layers configured to define at least one integrated electronic component. The integrated layers further define an integrated electron tunneling device, which includes first and second non-insulating layers spaced apart from one another such that a given voltage can be provided thereacross. The integrated electron tunneling device further includes an arrangement disposed between the first and second non-insulating layers and serving as a transport of electrons between and to the first and second non-insulating layers. The arrangement includes at least a first layer configured such that the transport of electrons includes, at least in part, transport by means of tunneling. The integrated electron tunneling device further includes an antenna structure connected with the first and second non-insulating layers, and the integrated electron tunneling device is electrically connected with the integrated electronic component.

Claims

1. An electro-optical device, comprising:

a formation of integrated layers, said integrated layers being configured so as to define at least one integrated electronic component; and

an electron tunneling device, said electron tunneling device including

first and second non-insulating layers spaced apart from one another such that a given voltage can be provided across the first and second non-insulating layers, and

an arrangement disposed between the first and second non-insulating layers and configured including at least one layer for supporting electron tunneling between and to said first and second non-insulating layers, and

an antenna structure that is formed, at least in part, from said first and second non-insulating layers as part of said tunneling device, and wherein said electron tunneling device is electrically connected with said integrated electronic component.

2. The electro-optical device of claim 1 wherein said electron tunneling device is configured such that using only said first layer in the arrangement would result in a given value of nonlinearity in said electron tunneling, with respect to said given voltage, and wherein said arrangement further includes a different, second layer disposed directly adjacent to and configured to cooperate with said first layer such that said nonlinearity, with respect to said given voltage, is increased ever and above said given value of nonlinearity by the inclusion of said second layer.

3. The electro-optical device of claim 2 wherein said first layer is formed of a first insulating material.

4. The electro-optical device of claim 3 wherein said first layer in said arrangement is formed of an amorphous, insulating material.

5. The electro-optical device of claim 3 wherein said second layer is formed of a different, second insulating material.

6. The electro-optical device of claim 1 wherein said integrated electron tunneling device is configured to form a rectifying element.

7. The electro-optical device of claim 1 wherein said integrated electron tunneling device is configured to form a Schottky diode.

8. The electro-optical device of claim 1 wherein said antenna structure is integrally formed from said first and second non-insulating layers.

9. The electro-optic device of claim 1 wherein said electron tunneling device is supported on a surface that is defined by said formation of integrated layers while being electrically connected with said integrated electronic component.

10. The electro-optical device of claim 1 wherein said electron tunneling device is integrally formed with said formation of integrated layers.