Transistor with reduced gate-to-source capacitance and method therefor
First Claim
1. A semiconductor device, comprising:
- an active region in a semiconductor substrate;
a gate finger over a channel in the active region and spaced from the channel by a gate dielectric having a first thickness, wherein the gate finger is of a first material;
a first gate tab adjacent to the gate finger, over the active region and spaced from the substrate by a first tab insulator having a second thickness, wherein the first gate tab is of the first material and the second thickness is greater than the first thickness, wherein the first material is conductive;
a second gate tab adjacent to the gate finger, over the active region and spaced from the substrate by a second tab insulator having the second thickness, wherein the second gate tab is of the first material;
a first tab connection electrically connecting the first gate tab to the gate finger, wherein the first tab connection is of the first material;
a second tab connection electrically connecting the second gate tab to the gate finger, wherein the second gate tab is of the first material; and
a gate bus electrically connected to the first and second gate tabs.
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Accused Products
Abstract
A power transistor, formed from transistors connected in parallel, each transistor is formed in an active region using a relatively long gate called a gate finger that is typically formed from polysilicon that accumulates resistance over its length. To alleviate this, the gate finger is strapped to a metal line at tabs adjacent to the finger gate over the active area, typically over the source, but the tabs add gate-to-source capacitance. This was previously quite small but as gate dielectrics have gotten thinner there is more capacitive coupling to the substrate by the tabs, and as gates have gotten thinner there is more resistance in the polysilicon finger gates. Both have the effect of increasing the RC time constant of the gate finger. This increase in RC time constant is alleviated by increasing the thickness of the dielectric separating the tabs from the substrate thereby reducing the capacitance caused by the tabs.
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Citations
23 Claims
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1. A semiconductor device, comprising:
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an active region in a semiconductor substrate; a gate finger over a channel in the active region and spaced from the channel by a gate dielectric having a first thickness, wherein the gate finger is of a first material; a first gate tab adjacent to the gate finger, over the active region and spaced from the substrate by a first tab insulator having a second thickness, wherein the first gate tab is of the first material and the second thickness is greater than the first thickness, wherein the first material is conductive; a second gate tab adjacent to the gate finger, over the active region and spaced from the substrate by a second tab insulator having the second thickness, wherein the second gate tab is of the first material; a first tab connection electrically connecting the first gate tab to the gate finger, wherein the first tab connection is of the first material; a second tab connection electrically connecting the second gate tab to the gate finger, wherein the second gate tab is of the first material; and a gate bus electrically connected to the first and second gate tabs. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A semiconductor device, comprising:
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a semiconductor substrate; a gate finger spaced from the substrate by a gate dielectric having a first thickness; a first gate tab adjacent to the gate finger and spaced from the substrate by a first tab insulator having a second thickness; a second gate tab adjacent to the gate finger and spaced from the substrate by a second tab insulator having the second thickness; a first tab connection connected to the first gate tab and the gate finger; a second tab connection connected to the second gate tab; and a gate bus connected to the first and second gate tabs. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19)
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20. In a semiconductor device having contacts to gate tabs over an active region and gate fingers spaced from the active region by a gate dielectric of a first thickness and connected to the gate tabs, the improvement comprising:
tab insulators between the tab connections and the substrate having a thickness greater than the gate dielectric. - View Dependent Claims (21, 22, 23)
Specification