Self-testing printed circuit board comprising electrically programmable three-dimensional memory

• US 7,126,196 B2
• Filed: 07/21/2004
• Issued: 10/24/2006
• Est. Priority Date: 10/07/2001
• Status: Expired due to Fees

• Current Assignee: Guobiao Zhang
• Original Assignee: Guobiao Zhang
• Inventors: Zhang, Guobiao
• Primary Examiner(s): Ngô, Ngân V.
• Application Number:
  US10/895,582
• Publication Number:
  US 20040262731A1
• Time in Patent Office: 825 Days
• Field of Search: 257/390, 257/700, 257/E27.102
• US Class Current: 257/390
• CPC Class Codes: G11C 17/06 using diode elements G11C17/14 takes precedence
• CPC Class Codes: G11C 17/14 in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
• CPC Class Codes: G11C 29/822 for read only memories
• CPC Class Codes: G11C 29/846 by choosing redundant lines at an output stage
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out
• CPC Class Codes: H01L 23/58 Structural electrical arrangements for semiconductor devices not otherwise provided for , e.g. in combination with batteries H01L23/49593, H01L23/49596 take precedence
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 29/76 Unipolar devices , e.g. field effect transistors

Abstract

The electrically programmable three-dimensional memory (EP-3DM) can be used to carry the test data and/or test-data seeds for the circuit-under-test (CUT). When integrated with the CUT, EP-3DM has minimum impact to the layout of the CUT. Apparently, CUT with integrated EP-3DM supports IC self-test. Moreover, with a large bandwidth with the CUT, EP-3DM-based IC self-test enables at-speed test.

Claims

1. A printed-circuit-board (PCB) supporting electrically-programmable three-dimensional memory (EP-3DM)-based self-test (EP-3DMST), comprising:

a first integrated circuit (IC) chip, comprising;

a substrate circuit, said substrate circuit further comprising a circuit-under-test (CUT) and a peripheral circuit;

an EP-3DM stacked on said substrate circuit and connected with said peripheral circuit through a plurality of inter-level connecting vias, said EP-3DM comprising at least an EP-3DM level;

wherein at least a portion of said EP-3DM stores at least of a portion of test data and/or test-data seeds for at least a portion of said CUT;

a second IC chip under-test, wherein at least a portion of said EP-3DM stores at least of a portion of test data and/or test-data seeds for at least a portion of said second IC chip under-test.

2. The PCB supporting EP-3DMST according to claim 1, further comprising a test interface for testing said EP-3DM.