Graphics processor and system with microcontroller for programmable sequencing of power up or power down operations
First Claim
1. A graphics processor, comprising:
- a set of registers storing register bits, wherein at least one of the register bits controls power being supplied to a flat panel display driven by the graphics processor; and
a microcontroller coupled to the registers and configured to selectively override the register bits, wherein the microcontroller is further configured to function as a sequencer for controlling the timing for power supplied to the flat panel display by executing a sequence of instructions, but is not configured to handle interrupts.
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Abstract
A graphics processor or display device including a microcontroller that functions as a sequencer, a computer system including at least one such graphics processor or display device, and a microcontroller for use in such a graphics processor or display device. In preferred embodiments, the microcontroller functions as a sequencer for controlling the timing of power up and/or power down operations by one or both of a graphics processor and a display device. The microcontroller is implemented to exclude any capacity to handle interrupts and so can provide guaranteed timing, and is preferably implemented to be small, simple, and programmable, and to store a small number of programs. Each program consists of instructions belonging to a small instruction set, such as a set consisting of set and clear instructions (for overriding or overwriting specified register bits) and wait, release, and stop instructions. When executing a program, the microcontroller typically overrides (in an ordered sequence) state and control bits that would otherwise be asserted.
22 Citations
20 Claims
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1. A graphics processor, comprising:
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a set of registers storing register bits, wherein at least one of the register bits controls power being supplied to a flat panel display driven by the graphics processor; and a microcontroller coupled to the registers and configured to selectively override the register bits, wherein the microcontroller is further configured to function as a sequencer for controlling the timing for power supplied to the flat panel display by executing a sequence of instructions, but is not configured to handle interrupts. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A graphics processor, comprising:
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a set of registers storing register bits, wherein at least one of the register bits controls power being supplied to a flat panel display driven by the graphics processor; a microcontroller coupled to the registers and configured to selectively overwrite the register bits, wherein the microcontroller is further configured to function as a sequencer for controlling the timing for power supplied to the flat panel display by executing a sequence of instructions, but is not configured to handle interrupts. - View Dependent Claims (9, 10, 11, 12)
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13. A system, including:
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a system bus; a CPU connected along the system bus; a graphics processor connected along the system bus; a frame buffer coupled to receive video data from the graphics processor; and a display device, coupled and configured to receive frames of the video data from the frame buffer and to produce a display in response thereto, wherein at least one of the graphics processor and the display device includes; a set of registers storing register bits, wherein at least one of the register bits controls power being supplied to the flat panel display; and a microcontroller coupled to the registers and configured to selectively override the register bits, wherein the microcontroller is further configured to function as a sequencer for controlling the timing with which power is supplied to the display by executing a sequence of instructions, but is not configured to handle interrupts. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20)
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Specification