Time-alignment apparatus and method for providing data frames of a plurality of channels with predeterminated time-offsets

• US 7,126,967 B2
• Filed: 06/23/2004
• Issued: 10/24/2006
• Est. Priority Date: 09/28/1999
• Status: Active Grant

• Current Assignee: Telefonaktiebolaget LM Ericsson
• Original Assignee: Telefonaktiebolaget LM Ericsson
• Inventors: Huaman-Bollo, Gian, Sönning, Raimund
• Primary Examiner(s): NGUYEN, HANH N
• Application Number:
  US10/873,171
• Publication Number:
  US 20040228338A1
• Time in Patent Office: 853 Days
• Field of Search: 370/400, 370/412, 370/350, 370/335, 370/381, 370/382, 370/383, 370/503, 370/506, 370/509, 370/510, 370/512, 370/411, 370/413, 370/329, 370/328, 370/395.71, 370/395.7
• US Class Current: 370/510
• CPC Class Codes: H04J 3/0632 Synchronisation of packets and cells, e.g. transmission of voice via a packet network, circuit emulation service [CES] queuing arrangements in packet switching elements H04L49/90; synchronising systems for the synchronous transmission of a pulse code modulated video signal with one or more other pulse code modulated signals H04N7/56

Abstract

The invention relates to a time-alignment apparatus and a time-alignment method of a transmitter (TX) of a telecommunication system TELE. Successive data frames (ch1/0, ch2/0, ch3/0, ch4/0, ch8/0, ch300/0) are written to one or two frame memories (RAM1, RAM2) starting at a respective frame start write address (FRST-ADR_chy). A third frame memory (RAM3) having a read state is read out in the column direction such that one data symbol of each storage resource (RES₁, RES₂ . . . RES₃₀₀) can be output to a modulator unit (BBTX) of the transmitter (TX). The read/write state (WR/RD) of the three frame memories (RAM1, RAM2, RAM3) is cyclically switched through a first to third alignment mode (M1, M2, M3) such that always a first write state memory (RAM1) and a second write state memory (RAM2) are provided. An interleaving process can be carried out together with the time-offset adjustment if the storage resource is constituted by an interleaving matrix. An efficient usage of storage space is obtained if the data bits forming one data symbol are stored together at one memory location of the respective storage resource. The invention is particularly relevant for a CDMA telecommunication system, in order to minimize the interference between the channels.

Claims

1. A time-alignment apparatus for use with a transmitter for a telecommunication system for receiving successive data frames, each frame containing a predetermined number of data symbols, respectively from a number of channels, and for successively outputting the data symbols with a predetermined time-offset relative to a synchronization clock, comprising:

first, second, and third read/write frame memories, each having a number of storage resources and storing the data symbols of one data frame of a respective channel, each frame memory having a write state in which data is written to said frame memory and a read state in which data is read from said frame memory;

a control unit for cyclically switching said frame memories through first, second, and third alignment modes synchronized to said synchronization clock such that;

in said first alignment mode, said first and second frame memories are in a write state and said third frame memory is in a read state;

in said second alignment mode, said second and third frame memories are in a write state and said first frame memory is in a read state; and

in said third alignment mode, said third and first frame memories are in a write state and said second frame memory is in a read state.

2. A time alignment apparatus of claim 1, further comprising:

a write/read address circuit for providing a respective frame start write address corresponding to said time-offset for each storage resource of a frame memory having a write state, and successive read addresses for all storage resources of a frame memory having a read state;

wherein after each mode switching, an input circuit is configured to start writing the data symbols of a newly arriving data frame of every channel into the respective storage resource of a first write state frame memory which was in a read state in the previous mode at the respective frame start write address, and to continue writing the data symbols into a corresponding storage resource of the other second frame memory having a write state at a write base address, if during the writing of the data symbols in said first frame memory the highest possible write address of the respective storage resource is reached; and

wherein an output circuit is configured to successively read one data symbol from the respective storage resources of said frame memory having a read state at said successive read addresses.

3. A time-alignment apparatus according to claim 2, wherein said data symbols respectively comprise a plurality of data bits output by a convolutional coder, and wherein said plurality of data bits are respectively stored together at one memory position of a respective matrix of said frame memories as determined by said write addresses.

4. A time-alignment apparatus according to claim 1, wherein each storage resource is constituted by a respective row of said frame memory when the data symbols are not interleaved, and wherein an output circuit is configured to read said data symbols successively along the column direction at said read addresses.

5. A time-alignment apparatus according to claim 1, wherein said write/read address circuit is configured to provide successive write addresses to enable said input circuit to write the data symbols of a respective data frame of a channel into the storage resource of one or more frame memories having a write state in an interleaving writing order such that the data symbols are stored in the row direction as sequential sets of data symbols corresponding to the data symbols in successive columns of said interleaving matrix.

6. A transmitter of a telecommunication system further comprising one or more time-alignment apparatus according to claim 1.

7. A transmitter according to claim 6, wherein said transmitter is a CDMA-transmitter.

8. A telecommunication system comprising one or more transmitters according to claim 6.

9. A telecommunication system according to claim 8, wherein said telecommunication system performs communications using a CDMA technique.

10. A time-alignment apparatus according to claim 1, wherein more than three frame memories are used and a cyclic switching is carried out with one frame memory having a read state and the other frame memories having a write state.

11. A method for time-aligning successive data frames, each frame containing a predetermined number of data symbols on a number of channels, and for successively outputting the data symbols with a predetermined time-offset relative to a synchronization clock, comprising:

writing data frames into first, second, and third read/write frame memories, each having a number of storage resources, each for storing the data symbols of one data frame of a respective channel, and each having a write state in which data is written to said frame memory and a read state in which data is read from said frame memory;

cyclically switching said frame memories through first, second, and third alignment modes synchronized to said synchronization clock, wherein;

in said first alignment mode, said first and second frame memories are in a write state and said third frame memory is in a read state;

in said second alignment mode, said second and third frame memories are in a write state and said first frame memory is in a read state; and

in said third alignment mode, said third and first frame memories are in a write state and said second frame memory is in a read state.

12. A method of claim 11, further comprising:

providing a respective frame start write address corresponding to said time-offset selectively for each storage resource of a frame memory having a write state, and successive read addresses commonly for all storage resources of a frame memory having a read state;

writing, after each mode switching, the data symbols of a newly arriving data frame of every channel into the respective storage resource of a first write state frame memory which was in a read state in the previous mode at the respective frame start write address, and continuing said writing of the data symbols into a corresponding storage resource of the other second frame memory having a write state a write base address, if during the writing of the data symbols in said first frame memory the highest possible write address of the respective storage resource is reached; and

successively reading one data symbol from the respective storage resources of said frame memory having a read state at said successive read addresses.

13. A method according to claim 12, wherein said data frames are written to a respective row of a respective frame memory when the data symbols are not interleaved, wherein said data symbols are successively read along the column direction at said read addresses.

14. A method according to claim 12, wherein said data symbols of a respective data frame of a channel are written into the storage resource of one or more frame memories having a write state in an interleaving writing order such that the data symbols are stored in the row direction as sequential sets of data symbols corresponding to the data symbols in successive columns of an interleaving matrix.

15. A method according to claim 12, wherein said data symbols respectively comprise a plurality of data bits output by a convolutional coder of an encoder, wherein said plurality of data bits are respectively stored together at one memory position of a respective matrix of said frame memories as determined by said write addresses.

16. A method according to claim 12, wherein more than three frame memories are used and a cyclic switching is carried out with one frame memory having a read state and the other frame memories having a write state.

17. A time-alignment apparatus for use with a transmitter of a telecommunication system for receiving successive data frames, each containing a predetermined number of data symbols, respectively from a number of channels, and for successively outputting the data symbols with a predetermined time-offset relative to a synchronization clock, comprising:

first, second, and third read/write frame memories, each having a number of storage resources, each for storing the data symbols of one data frame of a respective channel, and each having a write state in which data is written to said frame memory and a read state in which data is read from said frame memory;

a control unit for cyclically switching said frame memories through first, second, and third alignment modes synchronized to said synchronization clock such that;

in said first alignment mode, said first and second frame memories are in a read state and said third frame memory is in a write state;

in said second alignment mode, said second and third frame memories are in a read state and said first frame memory is in a write state; and

in said third alignment mode, said third and first frame memories are in a read state and said second frame memory is in a write state.

18. An apparatus of claim 17, further comprising:

a write/read address providing circuit for providing a respective frame start read address corresponding to said time-offset individually for each storage resource of a frame memory having a read state, and successive write addresses commonly for all storage resources of the frame memory having a write state;

wherein after each mode switching an input circuit is configured to successively write the data symbols of a newly arriving data frame of every channel into the respective storage resource of the frame memory having a write state at said successive write addresses; and

wherein an output circuit is configured to read one data symbol from the respective storage resources of a first frame memory which was in a write state in the previous mode at the respective frame start read address, and to continue reading the data symbols from a corresponding storage resource of the other second frame memory having a read state at a read base address, if during the reading of the data symbols in said first frame memory the highest possible read address of the respective storage resource is reached.

19. A method for time-aligning successive data frames, each containing a predetermined number of data symbols respectively from a number of channels, and for successively outputting the data symbols with a predetermined time-offset and for successively outputting the data symbols with a predetermined time-offset relative to a synchronization clock, comprising:

writing data frames into first, second, and third read/write frame memories, each having a number of storage resources, each for storing the data symbols of one data frame of a respective channel, and each having a write state in which data is written to said frame memory and a read state in which data is read from said frame memory;

cyclically switching said frame memories through first, second, and third alignment modes synchronized to said synchronization clock such that;

in said first alignment mode, said first and second frame memories are in a read state and said third frame memory is in a write state;

in said second alignment mode, said second and third frame memories are in a read state and said first frame memory is in a write state; and

in said third alignment mode, said third and first frame memories are in a read state and said second frame memory is in a write state.

20. A method of claim 19, further comprising:

providing a respective frame start read address corresponding to said time-offset selectively for each storage resource of a frame memory having a read state, and successive write addresses commonly for all storage resources of the frame memory having a write state;

successively writing after each mode switching the data symbols of a newly arriving data frame of every channel into the respective storage resource of the frame memory having a write state at said successive write addresses; and

reading one data symbol from the respective storage resources of a first frame memory which was in a write state in the previous mode at the respective frame start read address, and continuing the reading of the data symbols from a corresponding storage resource of the other second frame memory having a read state at a read base address, if during the reading of the data symbols in said first frame memory the highest possible read address of the respective storage resource is reached.

21. A time-alignment apparatus for use with a transmitter of a telecommunication system for receiving successive data frames each containing a predetermined number of data symbols respectively from a number of channels and for successively outputting the data symbols with a predetermined time-offset relative to a synchronization clock, comprising:

first, second, and third read/write frame memories, each having a number of storage resources, each for storing the data symbols of one data frame of a respective channel, and each having a write state in which data is written to said frame memory and a read state in which data is read from said frame memory;

a control unit for cyclically switching said frame memories through first, second, and third alignment modes synchronized to said synchronization clock such that;

in said first alignment mode, said first and second frame memories are in a write state and said third frame memory is in a read state;

in said second alignment mode, said second and third frame memory are in a write state and said first frame memory is in a read state; and

in said third alignment mode, said third and first frame memory are in a write state and said second frame memory is in a read state,

wherein more than three frame memories are used and a cyclic switching is carried out with one frame memory having a read state and the other frame memories having a write state.

22. A time alignment apparatus of claim 21, further comprising:

a write/read address providing circuit for providing a respective frame start write address corresponding to said time-offset individually for each storage resource of a frame memory having a write state, and successive read addresses commonly for all storage resources of a frame memory having a read state;

wherein after each mode switching, an input device starts writing the data symbols of a newly arriving data frame of every channel into the respective storage resource of a first write state frame memory which was in a read state in the previous mode at the respective frame start write address, and continues writing the data symbols into a corresponding storage resource of the other second frame memory having a write state at a write base address, if during the writing of the data symbols in said first frame memory the highest possible write address of the respective storage resource is reached; and

wherein an output device successively reads one data symbol from the respective storage resources of said frame memory having a read state at said successive read addresses.

23. A method for time-aligning successive data frames, each containing a predetermined number of data symbols on a number of channels, and for successively outputting the data symbols with a predetermined time-offset relative to a synchronization clock, comprising:

writing data frames into first, second, and third read/write frame memories each having a number of storage resources, each for storing the data symbols of one data frame of a respective channel, and each having a write state in which data is written to said frame memory and a read state in which data is read from said frame memory;

cyclically switching said frame memories through first, second, and third alignment modes synchronized to said synchronization clock, wherein;

in said first alignment mode, said first and second frame memories are in a write state and said third frame memory is in a read state;

in said second alignment mode, said second and third frame memories are in a write state and said first frame memory is in a read state; and

in said third alignment mode, said third and first frame memories are in a write state and said second frame memory is in a read state; and

wherein more than three frame memories are used and cyclic switching is carried out with one frame memory having a read state and the other frame memories having a write state.

24. A method of claim 23, further comprising:

providing a respective frame start write address corresponding to said time-offset selectively for each storage resource of a frame memory having a write state, and successive read addresses commonly for all storage resources of a frame memory having a read state;

writing, after each mode switching the data symbols of a newly arriving data frame of every channel into the respective storage resource of a first write state frame memory which was in a read state in the previous mode at the respective frame start write address, and continuing said writing of the data symbols into a corresponding storage resource of the other second frame memory having a write state a write base address, if during the writing of the data symbols in said first frame memory the highest possible write address of the respective storage resource is reached; and

successively reading one data symbol from the respective storage resources of said frame memory having a read state at said successive read addresses.