Shared memory architecture
First Claim
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1. A shared memory system architecture, comprising:
- a memory controller module;
first and second processor cores coupled to the memory controller module;
a first memory device coupled to the memory controller module by a first data bus;
a second memory device coupled to the memory controller module by a second data bus;
a shared address and control bus interconnecting the memory controller module and the first and second memory devices;
a group of shared memory space access registers defining access permission to shared memory space.
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Abstract
A wireless communications architecture having first and second synchronous memory devices coupled to a virtual channel memory controller by corresponding first and second data buses, and a shared address and control bus interconnecting the virtual channel memory controller and the first and second synchronous memory devices. The first and second synchronous memory devices are addressed with the shared address bus, and the first and second memory locations are accessed via the first and second data buses, respectively.
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Citations
23 Claims
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1. A shared memory system architecture, comprising:
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a memory controller module; first and second processor cores coupled to the memory controller module; a first memory device coupled to the memory controller module by a first data bus; a second memory device coupled to the memory controller module by a second data bus; a shared address and control bus interconnecting the memory controller module and the first and second memory devices; a group of shared memory space access registers defining access permission to shared memory space. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. The architecture of clam 1 further comprising:
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a first processor core memory access register block coupled to the first processor core; a second processor core memory access register block coupled to the second processor core; wherein the first processor core memory access register block and the second processor core memory access register block define memory access permission and enforce protected memory areas of the first and second processor cores.
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12. A method comprising:
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addressing first and second memory devices with a shared address bus interconnecting the first and second memory devices and a memory controller module; transferring data between the first memory device and the memory controller module on a first data bus; transferring data between the second memory device and the memory controller module on a second data bus; conveying access permission to shared memory space with a group of registers indicating shared memory space policy; facilitating communication between first and second processor cores with the shared memory space. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19)
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20. A shared memory system architecture, comprising:
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a memory controller module; first and second processor cores coupled to the memory controller module; wherein the memory controller module and the first and second processor cores are disposed on a single integrated circuit; a first memory device coupled to the memory controller module by a first data bus; a second memory device coupled to the memory controller module by a second data bus; a group of shared memory space access registers defining access permission to shared memory space, the group of shared memory space access registers disposed on the single integrated circuit. - View Dependent Claims (21, 22, 23)
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Specification