CMOS image sensor and manufacturing method thereof

• US 7,129,108 B2
• Filed: 09/30/2004
• Issued: 10/31/2006
• Est. Priority Date: 10/01/2003
• Status: Expired due to Fees

• Current Assignee: Columba Technologies, Inc. (Quarterhill Inc. (f/k/a Wi-LAN Inc.))
• Original Assignee: DONGBU ELECTRONICS CO., LTD. (DB HiTek Co., Ltd.)
• Inventors: Jang, Hoon
• Primary Examiner(s): WOJCIECHOWICZ, EDWARD JOSEPH
• Application Number:
  US10/956,202
• Publication Number:
  US 20050082627A1
• Time in Patent Office: 761 Days
• Field of Search: 257/225, 438/70
• US Class Current: 438/70
• CPC Class Codes: H01L 27/14621 Colour filter arrangements
• CPC Class Codes: H01L 27/14636 Interconnect structures
• CPC Class Codes: H01L 27/14685 Process for coatings or optical elements

Abstract

A CMOS image sensor according to the present invention includes a substrate having a light receiving region, an interlayer insulating film formed on the substrate, a plurality of metal wirings formed on the interlayer insulating film so as to expose the light receiving region, a protection layer coated on the metal wirings and the interlayer insulating film, and a plurality of color filters formed on the protection layer, wherein at least one of the color filters is provided with an isolation layer formed on an upper surface thereof.

Claims

1. A method for manufacturing a CMOS image sensor comprising:

forming an interlayer insulating film on a substrate having a light receiving region;

forming a plurality of metal wirings so as to expose the light receiving region on the interlayer insulating film between the metal wirings;

forming a protection layer on the metal wirings and the interlayer insulating film;

forming a first color filter on the protection layer;

forming a first isolation layer on the first color filter and the protection layer; and

forming a second color filter on the first isolation layer;

forming a second isolation layer on the second color filter and the first isolation layer;

forming a third color filter on the second isolation layer; and

forming a third isolation layer on the third color filter.

2. The method of claim 1, further comprising exposing a pad part of the metal wirings after forming the third isolation layer.

3. The method of claim 1, wherein forming the first to third isolation layers comprises a chemical vapor deposition technique or spin coating technique.

4. The method of claim 3, wherein forming a first one of the first to third color filters comprises a blue color filter, a second one of the first to third color filters comprises a red color filter, and a third one of the first to third color filters comprises a green color filter.

5. The method of claim 4, wherein the first color filter comprises a blue color filter, the second color filter comprises a red color filter, and the third color filter comprises a green color filter.

6. The method of claim 1, further comprising forming a field oxide layer and a transistor gate electrode on the substrate.

7. The method of claim 6, wherein the substrate comprises a semiconductor substrate.

8. The method of claim 1, wherein each of the first to third isolation layers independently comprises a thermal oxide layer, a silicon nitride layer, a TEOS layer, a silicon oxide layer, or a silicon oxide nitride layer.

9. The method of claim 1, wherein each or the first to third isolation layers independently has a thickness in a range of 50˜

3000 Å

.

10. The method of claim 1, wherein the first isolation layer is formed such that it is between the first color filter and the second color filter.

11. A method for manufacturing a CMOS image sensor comprising:

forming an interlayer dielectric layer on a substrate having a light receiving region;

forming a plurality of metal wirings so as to expose the light receiving region on the interlayer dielectric layer between the metal wirings;

forming a protection layer on the metal wirings and the interlayer dielectric layer;

forming a first color filter an the protection layer;

forming a first isolation layer on the first color filter and the protection layer;

forming a second color filter on the first isolation layer;

forming a third color filter on the first isolation layer; and

forming a second isolation layer on the second color filter, the third color filter, and the first isolation layer.

12. The method of claim 11, further comprising exposing a pad part of the metal wirings after forming the second isolation layer.

13. The method of claim 11, wherein forming each of the first and second isolation layers comprises a chemical vapor deposition technique or spin coating technique.

14. The method of claim 11, wherein forming a first one of the first to third color filters comprises a blue color filter, a second one of the first to third color filters comprises a red color filter, and a third one of the first to third color filters comprises a green color filter.

15. The method of claim 14, wherein the first color filter comprises a blue color filter, the second color filter layer comprises a red color filter, and the third color filter comprises a green color filter.

16. The method of claim 11, further comprising forming a field oxide layer and a transistor gate electrode on the substrate.

17. The method of claim 16, wherein the substrate comprises a semiconductor substrate.

18. The method of claim 11, wherein each of the first and second isolation layers independently comprises a thermal oxide layer, a silicon nitride layer, a TEOS layer, a silicon oxide layer, or a silicon oxide nitride layer.

19. The method of claim 11, wherein each of the first and second isolation layers independently has a thickness in a range of 50˜

3000 Å

.

20. The method of claim 11, wherein the first isolation layer is formed such that it is between the first color filter and each of the second and third color filters.