Semiconductor device and method for manufacturing the same

• US 7,129,110 B1
• Filed: 08/22/2000
• Issued: 10/31/2006
• Est. Priority Date: 08/23/1999
• Status: Expired due to Term

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: ROHM Co., Ltd.
• Inventors: Shibata, Kazutaka
• Primary Examiner(s): Gupta, Yogendra N.
• Assistant Examiner(s): Song, Matthew J.
• Application Number:
  US09/830,092
• Time in Patent Office: 2,261 Days
• Field of Search: 257/737, 257/777, 257/778, 438/108, 438/109, 438/113, 438/459, 438/465, 438/613, 438/106
• US Class Current: 438/106
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/274 by blanket deposition of the material of the layer connector
• CPC Class Codes: H01L 2224/73209 Bump and HDI connectors
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/0652 Bump or bump-like direct electrical connections from substrate to substrate
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 2225/06572 Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 24/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0655 the devices being arranged next to each other
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/0102 : Calcium [Ca]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01041 : Niobium [Nb]
• CPC Class Codes: H01L 2924/01043 : Technetium [Tc]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15331 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/18161 : of a flip chip
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/3511 : Warping

Abstract

A method for manufacturing a semiconductor device having projection electrodes on the surface of a semiconductor substrate. This method include an electrode forming step of forming the projection electrodes on the surface of the semiconductor substrate, a step of forming a protective resin layer on the whole surface of the semiconductor substrate provided with the projection electrodes, a back side grinding step of thinning the semiconductor substrate by polishing or grinding the back side of the semiconductor substrate, and a surface grinding step of exposing the projection electrodes by polishing or grinding the surface side of the semiconductor substrate.

Claims

1. A method for manufacturing a semiconductor device, comprising:

a step of forming projection electrodes on a surface at a front side of a semiconductor substrate,

after said step of forming projection electrodes, a step of forming a surface resin layer on the surface of the semiconductor substrate,

a step of forming a back side resin layer on a back side of the semiconductor substrate so that the surface resin layer and the back side resin layer have substantially the same thickness respectively,

a surface grinding step of exposing the projection electrodes from the surface resin layer by polishing or grinding the surface resin layer,

bracing the substrate with the back side resin layer until after the surface grinding step, and

after said surface grinding step, a back side grinding step of thinning the semiconductor substrate by removing the back side resin layer, through polishing or grinding, from the semiconductor substrate provided with the surface resin layer and the back side resin layer, and by further polishing or grinding the back side of the semiconductor substrate from which the back side resin layer has been removed.

2. A method for manufacturing a semiconductor device as claimed in claim 1, further comprising a cutting out step of cutting out pieces of semiconductor devices by cutting the semiconductor substrate along cutting lines after completing the back side grinding step.

3. A method for manufacturing a semiconductor device as claimed in claim 1, in which the surface resin layer is formed in such a manner that the projection electrodes are embedded in the surface resin layer.

4. A method for manufacturing a semiconductor device as claimed in claim 1, further comprising a cutting out step of cutting out pieces of semiconductor devices by cutting the semiconductor substrate along cutting lines after completing the back side grinding step, wherein the surface grinding step includes exposing the projection electrodes from the surface resin layer by polishing or grinding the surface resin layer such that the remaining surface layer has a thickness that is uniform at least within the cutting lines defining the individual pieces cut out of semiconductor devices in the cutting out step.

5. A method for manufacturing a semiconductor device as claimed in claim 1, wherein said step of forming a surface resin layer includes forming the surface layer with uniform thickness.

6. A method for manufacturing a semiconductor device as claimed in claim 1, wherein the surface grinding step includes grinding the surface resin layer so that the heights of the plurality of projection electrodes are uniform.

7. A method for manufacturing a semiconductor device, comprising:

a chip bonding step of bonding a plurality of semiconductor chips face-down onto a surface of a semiconductor substrate with active surfaces of the semiconductor chips opposed to the surface of the semiconductor substrate, in such a manner that the plurality of semiconductor chips and substrate define chip-on-chip structures,

an electrode forming step of forming a plurality of projection electrodes on the surface of the semiconductor substrate, including forming each of the projection electrodes with a height such that the top end each projection electrode is between the height of the active surface of the semiconductor chips and a height of an inactive surface of the semiconductor chips,

a resin sealing step of sealing, with a protective resin, the semiconductor chips and the exposed surface of the semiconductor substrate after forming the projection electrodes in such a manner that head portions of the projection electrodes are exposed, and

a cutting out step of taking out individual pieces of chip-on-chip type semiconductor devices by cutting the semiconductor substrate along predetermined cutting lines.

8. A method for manufacturing a semiconductor device as claimed in claim 7, in which the resin sealing step includes an electrode exposing step of exposing the head portions of the projection electrodes by removing a surface layer section of the protective resin.

9. A method for manufacturing a semiconductor device as claimed in claim 8, in which the electrode exposing step includes a chip grinding step of simultaneously polishing or grinding the protective resin and an inactive surface side of the semiconductor chips.

10. A method for manufacturing a semiconductor device as claimed in claim 7, in which a back side of the semiconductor substrate or an inactive surface side of the semiconductor chips is polished or ground before the cutting out step.

11. A method for manufacturing a semiconductor device as claimed in claim 7, wherein the semiconductor substrate includes a semiconductor wafer and the method is performed a wafer level basis.