Manufacturing method for semiconductor device, semiconductor device, and electronic apparatus

• US 7,129,112 B2
• Filed: 02/06/2004
• Issued: 10/31/2006
• Est. Priority Date: 03/25/2003
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Seiko Epson Corporation (Seiko Group)
• Inventors: Matsuo, Yoshihide
• Primary Examiner(s): Lebentritt, Michael
• Assistant Examiner(s): STEVENSON, ANDRE C
• Application Number:
  US10/774,362
• Publication Number:
  US 20050029630A1
• Time in Patent Office: 998 Days
• Field of Search: 438/400, 438/401, 438458-460, 438/466, 438/469, 438/478, 438/763, 438/48, 438/55, 438/68, 438/69, 438/7, 438/13, 438 14- 17, 438 23- 25, 438/29, 438/101, 438/107, 438/109, 438/110, 438/142, 438/149, 438/167, 438/171, 438/186, 438/353, 257/270
• US Class Current: 438/107
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/3083 characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/03 Manufacturing methods
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/11 Manufacturing methods
• CPC Class Codes: H01L 2224/13009 Bump connector integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13019 at the bonding interface of the bump connector, i.e. on the surface of the bump connector
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/16146 the bump connector connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81193 wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81815 Reflow soldering
• CPC Class Codes: H01L 2224/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/181 : Encapsulation

Abstract

A manufacturing method for a semiconductor device includes a hole portion formation step for forming hole portions whose entire width is substantially identical to the width of the opening portion in a part of the active surface side of the substrate on which electronic components are formed, a curved surface formation step for curving the bottom surface of the hole portion while maintaining the width of the bottom surface in the hole portions substantially identical to the width of the opening portion, a connecting terminal formation step for forming connecting terminals that serve as the external electrodes of the electronic circuits by burying metal in the hole portions, and an exposure step for exposing a part of the connecting terminals by carrying out processing on the back surface of the substrate.

Claims

1. A manufacturing method for a semiconductor device comprising:

a hole portion formation step for forming hole portions whose entire width is substantially identical to the width of the opening portion in a part of the active surface side of the substrate on which electronic components are formed;

a curved surface formation step for curving the bottom surface of the hole portion while maintaining the width of the bottom surface in the hole portions substantially identical to the width of the opening portion;

a connecting terminal formation step for forming connecting terminals that serve as the external electrodes of the electronic circuits by burying metal in the hole portions;

an exposure step for exposing a part of the connecting terminals by carrying out processing on the back surface of the substrate; and

an insulating film formation step of forming an insulating film on the inner wall and the bottom surface of the hole portions between the curved surface formation step and the connecting terminal formation step, and further

the exposure step comprising;

a first etching step for etching the back surface of the substrate until the thickness of the substrate is approximately slightly thicker than the burying depth of the connecting terminals;

a second etching step for exposing the insulating film formed in the hole portions by etching the back surface of the substrate at an etching rate that is lower than the etching rate in the first etching step; and

a third etching step for exposing the connecting terminals by etching at least a part of the exposed insulating film.

2. A manufacturing method for a semiconductor device comprising:

a concavo-convex shape formation step for forming a concavo-convex shape on a part of the active surface side of the substrate on which the electronic circuits are formed;

a hole formation step for forming hole portions by etching the area in which the concavo-convex shape has been formed, whose entire width is substantially equal to the width of the area on which the concavo-convex shape has been formed and whose bottom surface has a shape substantially identical to the concavo-convex shape;

a connecting terminal formation step for forming the connecting terminals that serve as the external electrodes of the electronic circuits by burying metal in the hole portions;

an exposure step for exposing a part of the connecting terminals by carrying out processing of the back surface of the substrate; and

an insulating film formation step for forming an insulating film on the inner wall and the bottom surface of the hole portions between the hole formation step and the connecting terminal formation step, and further

the exposure step comprising;

a first etching step for etching the back surface of the substrate until the thickness of the substrate is approximately slightly thicker than the burying depth of the connecting terminals;

a second etching step for exposing the insulating film formed in the hole portions by etching the back surface of the substrate at an etching rate that is lower than the etching rate in the first etching step; and

a third etching step for exposing the connecting terminals by etching at least a part of the exposed insulating film.

3. A manufacturing method for a semiconductor device comprising:

a mask formation step for forming a mask having a plurality of holes in the hole formation area set in a part of the active surface side of the substrate on which the electronic circuits are formed;

a concavo-convex shape hole formation step for forming hole portions whose entire width is substantially identical to the width of the hole formation area and whose bottom surface has a concavo-convex shape by etching the substrate through each of the holes formed in the mask using an etching method in which the holes widen slightly in the surface direction of the substrate;

a connecting terminal formation step for forming connecting terminals that serve as the external electrodes for the electronic circuits by burying metal in the hole portions;

an exposure step for exposing a part of the connecting terminals by carrying our processing on the back surface of the substrate; and

an insulating film formation step for forming an insulating film on the inner wall and the bottom surface of the hole portions between the concavo-convex hole formation step and the connecting terminal formation step, and further

the exposure step comprising;

a first etching step for etching the back surface of the substrate until the thickness of the substrate is approximately slightly thicker than the burying depth of the connecting terminals;

a second etching step for exposing the insulating film formed in the hole portions by etching the back surface of the substrate at an etching rate that is lower than the etching rate in the first etching step; and

a third etching step for exposing the connecting terminals by etching at least a part of the exposed insulating film.