Method and structure for forming strained Si for CMOS devices

• US 7,129,126 B2
• Filed: 11/05/2003
• Issued: 10/31/2006
• Est. Priority Date: 11/05/2003
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Yang, Haining S., Zhang, Ying, Steegen, An L.
• Primary Examiner(s): Smoot, Stephen W.
• Application Number:
  US10/605,906
• Publication Number:
  US 20050093076A1
• Time in Patent Office: 1,091 Days
• Field of Search: 438/218
• US Class Current: 438/199
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/0243 Surface structure
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02658 Pretreatments cleaning in general H01L21/02041
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/2658 of a molecular ion, e.g. decaborane
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/76232 of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls H01L21/76229 takes precedence
• CPC Class Codes: H01L 21/76283 Lateral isolation by refilling of trenches with dielectric material
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66575 where the source and drain or source and drain extensions are self-aligned to the sides of the gate H01L29/66606 takes precedence
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7842 means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate variation of the composition of the channel H01L29/1054
• CPC Class Codes: H01L 29/7846 the means being located in the lateral device isolation region, e.g. STI
• CPC Class Codes: H01L 29/7849 : the means being provided under the channel

Abstract

A method for manufacturing a device including an n-type device and a p-type device. In an aspect of the invention, the method involves doping a portion of a semiconductor substrate and forming a gap in the semiconductor substrate by removing at least a portion of the doped portion of the semiconductor substrate. The method further involves growing a strain layer in at least a portion of the gap in the semiconductor substrate. For the n-type device, the strain layer is grown on at least a portion which is substantially directly under a channel of the n-type device. For the p-type device, the strain layer is grown on at least a portion which is substantially directly under a source region or drain region of the p-type device and not substantially under a channel of the p-type device.

Claims

1. A method for manufacturing a device including an n-type device and a p-type device, comprising:

doping a portion of a semiconductor substrate;

forming a gap in the semiconductor substrate by removing at least a portion of the doped portion of the semiconductor substrate;

depositing a spacer material over portions of the gap; and

growing a strain layer in at least a portion of the gap in the semiconductor substrate.

2. The method of claim 1, wherein the strain layer is grown on at least a portion which is substantially directly under a channel of the n-type device.

3. The method of claim 1, wherein the strain layer is grown on at least a portion which is substantially directly under at least one of a source region or drain region of the p-type device.

4. The method of claim 3, wherein the strain layer is not grown under a channel of the p-type device.

5. The method of claim 1, further comprising/depositing a patterned photo-resist layer on a semiconductor substrate, wherein the step of depositing comprises:

depositing a photo-resist layer which covers a portion of the semiconductor substrate which is to be under a channel of the p-type device.

6. The method of claim 5, wherein the photo-resist layer exposes a portion of the semiconductor substrate which is to be under a channel of the n-type device.

7. The method of claim 5, further comprising removing the deposited patterned photo-resist layer.

8. The method of claim 7, further comprising depositing a mask on the semiconductor substrate.

9. The method of claim 8, further comprising patterning the deposited mask such that a portion of the semiconductor substrate is covered and a portion of the semiconductor substrate is exposed.

10. The method of claim 9, wherein the step of forming a gap comprises etching the exposed portion of the semiconductor substrate to selectively expose a side-wall of at least a portion of the doped portion of the semiconductor substrate.

11. The method of claim 10, wherein the spacer material is deposited over the semiconductor substrate.

12. The method of claim 11, wherein the depositing of the spacer material includes depositing the spacer material on exposed portions of the gap.

13. The method of claim 12, further comprising filling unexposed portions of the gap with oxide material.

14. The method of claim 1, wherein the gap is a tunnel formed under the channel of the n-type device.

15. The method of claim 1, wherein the step of doping comprises doping the semiconductor substrate with Ge.

16. The method of claim 15, wherein the doping concentration of the Ge is about 1×

10¹⁴ Ge/cm2 to about 1×

10¹⁶ Ge/cm2.

17. The method of claim 1, wherein the step of doping comprises doping the semiconductor substrate with at Feast one of As, B, In, and Sb.

18. The method of claim 1, wherein the step of growing a strain layer comprises growing at least one of SiGe, Si₃N₄, SiO₂ and SiO_xN_yin at east a portion of the gap in the semiconductor substrate.

19. The method of claim 1, wherein the strain layer is grown on at least a portion that is substantially devoid of the spacer material.

20. A method for manufacturing a device including an n-type device and a p-type device, comprising:

growing a first strain layer on a semiconductor substrate;

growing a silicon aver above the first strain layer;

forming a gap between the semiconductor substrate and the silicon layer by removing at least a portion of the silicon layer and the first strain layer from above the semiconductor substrate; and

growing a second strain layer in the gap,

wherein the second strain layer is grown on at least a portion which is substantially directly under a channel of the n-type device.

21. A method for manufacturing a device including an n-type device and a p-type device, comprising:

growing a first strain layer on a semiconductor substrate;

growing a silicon layer above the first strain layer;

forming a gap between the semiconductor substrate and the silicon layer by removing at least a portion of the silicon layer and the first strain layer from above the semiconductor substrate; and

growing a second strain layer in the gap,

wherein the second strain layer is grown on at least a portion which is substantially directly under at least one of a source region or drain region of the p-type device.