Method and structure of memory element plug with conductive Ta removed from sidewall at region of memory element film

• US 7,129,133 B1
• Filed: 09/13/2004
• Issued: 10/31/2006
• Est. Priority Date: 09/13/2004
• Status: Active Grant

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Spansion LLC (Infineon Technologies AG)
• Inventors: Tran, Minh, Avanzino, Steven C.
• Primary Examiner(s): Fourson, George
• Assistant Examiner(s): GARCIA, JOANNIE A
• Application Number:
  US10/939,773
• Time in Patent Office: 778 Days
• Field of Search: 438/243, 438/244, 438/253, 438/386, 438/387, 438/396, 438/FOR.220, 438/FOR.430, 438/239, 438/240, 438/3, 257/296, 257/301, 257/303, 257/306, 257/532, 257/E27.084, 257/E21.646, 257/77, 257/310
• US Class Current: 438/244
• CPC Class Codes: H10B 63/80 Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
• CPC Class Codes: H10K 10/50 Bistable switching devices
• CPC Class Codes: H10K 19/00 Integrated devices, or assemblies of multiple devices, comprising at least one organic element specially adapted for rectifying, amplifying, oscillating or switching, covered by group H10K10/00
• CPC Class Codes: H10N 70/066 by filling of openings, e.g. damascene method
• CPC Class Codes: H10N 70/245 the species being metal cations, e.g. programmable metallization cells
• CPC Class Codes: H10N 70/801 Constructional details of multistable switching devices
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/8833 Binary metal oxides, e.g. TaOx

Abstract

Disclosed are methods and structures for fabrication of reliable and efficient memory cells. The methods involve formation of a conformal diffusion barrier layer in a via, deposition of an electrode material in the via, removal of a certain portion of the electrode material from the via to expose a the portion of the diffusion barrier layer, converting the exposed portion of the diffusion barrier layer into an oxide, forming a memory element film, and forming and patterning a top electrode. Improved electrical conduction and data retention from the memory element of a memory cell by preventing short circuits and leakage of current through the conductive diffusion barrier layer, and thereby enhanced reliability and performance of a memory cell are obtained.

Claims

1. A method for fabricating a memory element comprising:

forming a diffusion barrier layer over an opening formed in a dielectric layer of a semiconductor substrate;

depositing an electrode material into the opening;

recessing a portion of the electrode material from the opening to expose a portion of the diffusion barrier layer using a wet etch;

oxidizing the exposed portion of the diffusion barrier layer;

forming memory element films over the electrode material, the memory element films comprising a passive layer and an active layer; and

forming a top electrode over the memory element films.

2. The method claim 1, wherein the electrode material deposited into the opening comprises a metal.

3. The method of claim 1, wherein the electrode material deposited into the opening comprises copper.

4. The method of claim 1, wherein the diffusion barrier layer comprises at least one of tantalum, compounds of tantalum, and alloys of tantalum.

5. The method of claim 1, wherein the diffusion barrier layer has a thickness from about 5 Å

to about 50 Å

.

6. The method of claim 1, wherein the oxidation of the diffusion barrier layer is carried out using a technique selected from the group consisting of thermal oxidation, anodic oxidation, chemical oxidation, reactive ion etch, implantation, and wet etch.

7. The method claim 1, wherein recessing the electrode material in the opening and oxidizing the exposed portion of the diffusion barrier layer occur simultaneously.

8. The method of claim 1, wherein oxidizing the exposed portion of the diffusion barrier layer occurs subsequent to recessing of the electrode material from the opening.

9. The method of claim 1, further comprising forming a thin conductive metal barrier layer over the memory element films.

10. The method of claim 1, wherein the wet etch is performed by using an acid based etchant.

11. The method of claim 1, wherein the wet etch is performed by using a peroxide based etchant.

12. The method of claim 1, wherein oxidizing the exposed portion of the diffusion barrier layer comprises oxidizing tantalum to a tantalum oxide.

13. The method of claim 1, wherein the passive layer comprises copper sulfide.

14. The method of claim 1, wherein the active layer comprises a semiconducting polymer.

15. A memory cell comprising:

a bottom electrode;

a memory element film over the bottom electrode;

a top electrode over the memory element film;

a thin conductive metal barrier layer between the memory element film and the top electrode, the thin conductive barrier layer having a thickness from about 10 Å

to about 200 Å

, and

a diffusion barrier layer at least partially surrounding the bottom electrode, the memory element film, the thin conductive metal barrier layer, and the top electrode,

wherein the diffusion barrier layer adjacent the memory element film and the top electrode comprises an oxidized diffusion barrier metal.

16. The memory cell of claim 15, wherein the diffusion barrier layer has a thickness from about 5 Å

to about 50 Å

.

17. The memory cell of claim 15, wherein the bottom electrode comprises copper.

18. The memory cell of claim 15, wherein the memory film comprises a passive layer and an active layer.

19. The memory cell of claim 18, wherein the passive layer comprises copper sulfide.

20. The memory cell of claim 18, wherein the active layer comprises a semiconducting polymer.

21. The memory cell of claim 15, wherein the diffusion barrier layer comprises tantalum oxide and at least one of tantalum, compounds of tantalum, and alloys of tantalum.

22. A memory cell comprising:

a bottom electrode;

a memory element film over the bottom electrode, wherein the memory element film comprises a passive layer and an active layer, the passive layer comprising copper sulfide;

a top electrode over the memory element film, and

a diffusion barrier layer at least partially surrounding the bottom electrode, the memory element film, and the top electrode,

wherein the diffusion barrier layer adjacent the memory element film and the top electrode comprises an oxidized diffusion barrier metal.