Method and structure to improve reliability of copper interconnects

• US 7,129,165 B2
• Filed: 06/01/2004
• Issued: 10/31/2006
• Est. Priority Date: 02/04/2003
• Status: Active Grant

• Current Assignee: Novellus Systems Incorporated (Lam Research Corporation)
• Original Assignee: ASM NuTool, Inc. (ASM International NV)
• Inventors: Basol, Bulent M., Talieh, Homayoun
• Primary Examiner(s): VU, HUNG K
• Application Number:
  US10/858,766
• Publication Number:
  US 20040219779A1
• Time in Patent Office: 882 Days
• Field of Search: 438/638, 438/643, 438/663, 438/687
• US Class Current: 438/663
• CPC Class Codes: H01L 21/2885 using an external electrical current, i.e. electro-deposition
• CPC Class Codes: H01L 21/7684 Smoothing; Planarisation
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76864 Thermal treatment
• CPC Class Codes: H01L 21/76873 for electroplating
• CPC Class Codes: H01L 21/76874 for electroless plating
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 23/53228 the principal metal being copper
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method of forming a conductor structure on a surface of a wafer is provided. The surface of the wafer includes cavities separated by field regions. Initially, a barrier layer is deposited on the surface that includes cavities separated by field regions. A thin seed layer with a substantially uniform thickness is deposited on the barrier layer. The barrier layer and the seed layer portions in the cavities occupy less than 30% of the volume of each cavity. The remaining volume of each cavity is filled with a conductive material which is formed on the seed layer. The conductive layer has a substantially small thickness. After forming the conductive layer, the wafer is annealed to increase grain size in the conductive layer and the seed layer.

Claims

1. A method of forming a conductor structure on a surface of a wafer, the surface including cavities separated by field regions, the method comprising:

depositing a seed layer with a substantially uniform thickness on the field regions and in the cavities of the surface having a barrier layer thereon, wherein the barrier layer and the seed layer portions in the cavities occupy less than 30% of the volume of each cavity;

forming a conductive layer by electrodepositing a conductive material on the seed layer, wherein the conductive material fills the remaining volume of each cavity and wherein a thickness of the conductive layer over the field regions is between about 100 nm and about 200 nm; and

annealing the wafer to increase grains size in the conductive layer and the seed layer.

2. The method of claim 1 further comprising the step of reducing the thickness of the conductive layer in a planar manner so that the conductive layer thickness over the field regions is about 2 to 20 times the thickness of the seed layer thickness.

3. The method of claim 2, wherein the thickness of the conductive layer is reduced using a chemical mechanical polishing process.

4. The method of claim 2, wherein the thickness of the conductive layer is reduced using an electrochemical mechanical polishing process.

5. The method of claim 2, further comprising the step of removing the conductive layer until the barrier layer on the field regions is exposed and the conductive material is confined in the cavities.

6. The method of claim 5, further comprising the step of removing the barrier layer from the field regions.

7. The method of claim 1, wherein the step of depositing comprises depositing the seed layer having a thickness in the range of less than 30 nanometers.

8. The method of claim 1, wherein the step of forming the conductive layer is performed using an electrochemical deposition.

9. The method of claim 1, wherein the step of forming the conductive layer is performed using an electrochemical mechanical deposition.

10. The method of claim 1, wherein the conductive material is copper.

11. The method of claim 1, wherein the step of annealing is performed in a temperature range of 200°

–

300°

C.

12. The method of claim 1, wherein the step of annealing is performed using a rapid thermal annealing system processing one wafer at a time.

13. A method of forming a conductor structure on a surface of a wafer, the surface including cavities separated by field regions, the method comprising:

depositing a seed layer with a substantially uniform thickness on the field regions and in the cavities of the surface having a barrier layer thereon, wherein the barrier layer and the seed layer portions in the cavities occupy less than 30% of the volume of each cavity;

forming a substantially planar conductive layer by depositing a conductive material on the seed layer, wherein the conductive material fills the remaining volume of each cavity and wherein a thickness of the conductive layer over the field regions is between about 100 nm and about 200 nm and is about 2 to 20 times the thickness of the seed layer thickness; and

annealing the wafer to form large grains in the conductive layer and the seed layer.

14. The method of claim 13, wherein the step of forming the substantially planar conductive layer is performed using an electrochemical mechanical deposition.

15. The method of claim 13, further comprising the step of removing the planar conductive layer until the barrier layer on the field regions is exposed and the conductive material is confined in the cavities.

16. The method of claim 15, wherein the step of removing the planar conductive layer is performed using a chemical mechanical polishing process.

17. The method of claim 15, further comprising the step of removing the barrier layer from the field regions.

18. The method of claim 13, wherein the step of depositing comprises depositing the seed layer having a thickness in the range of less than 30 nanometers.

19. The method of claim 13, wherein the conductive material is copper.

20. The method of claim 13, wherein the step of annealing is performed in a temperature range of 200°

–

300°

C.

21. The method of claim 13, wherein the step of annealing is performed using a rapid thermal annealing system processing one wafer at a time.