Dense arrays and charge storage devices

• US 7,129,538 B2
• Filed: 05/10/2004
• Issued: 10/31/2006
• Est. Priority Date: 08/14/2000
• Status: Expired due to Term

• Current Assignee: Woden Technologies Inc. (Wi-LAN Inc.)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Cleeves, James M., Herner, Brad, Subramanian, Vivek, Lee, Thomas H., Johnson, Mark G., Walker, Andrew J., Kouznetzov, Igor G., Petti, Christopher, Farmwald, Paul M.
• Primary Examiner(s): Weiss, Howard
• Application Number:
  US10/842,008
• Publication Number:
  US 20040206996A1
• Time in Patent Office: 904 Days
• Field of Search: 257/321
• US Class Current: 257/321
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 2211/5612 Multilevel memory cell with more than one floating gate
• CPC Class Codes: H01L 21/31053 involving a dielectric removal step
• CPC Class Codes: H01L 21/76819 Smoothing of the dielectric planarisation of insulating materials per se H01L21/31051
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/0626 with a localised breakdown region, e.g. built-in avalanching region in self-protected thyristors H01L29/7424
• CPC Class Codes: H01L 29/0661 specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/16 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/1604 Amorphous materials
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/42332 with the floating gate formed by two or more non connected parts, e.g. multi-particles flating gate
• CPC Class Codes: H01L 29/42364 : characterised by the insulating layer, e.g. thickness or uniformity H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/511 : with a compositional variation, e.g. multilayer structures H01L29/516 takes precedence
• CPC Class Codes: H01L 29/513 : the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 : the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/518 : the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66825 : with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/66833 : with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/7391 : Gated diode structures
• CPC Class Codes: H01L 29/78642 : Vertical transistors
• CPC Class Codes: H01L 29/7881 : Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H01L 29/7889 : Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H01L 29/792 : with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H01L 29/7926 : Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H01L 29/861 : Diodes
• CPC Class Codes: H01L 29/8616 : Charge trapping diodes
• CPC Class Codes: H10B 20/00 : Read-only memory [ROM] devices
• CPC Class Codes: H10B 20/60 : Peripheral circuit regions
• CPC Class Codes: H10B 41/20 : characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/27 : the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/30 : characterised by the memory core region
• CPC Class Codes: H10B 41/40 : characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/60 : the control gate being a doped region, e.g. single-poly memory cell
• CPC Class Codes: H10B 43/10 : characterised by the top-view layout
• CPC Class Codes: H10B 43/20 : characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/23 : with source and drain on different levels, e.g. with sloping channels
• CPC Class Codes: H10B 43/27 : the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/30 : characterised by the memory core region
• CPC Class Codes: H10B 43/40 : characterised by the peripheral circuit region
• CPC Class Codes: H10B 69/00 : Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.

Claims

1. A three dimensional nonvolatile device array, comprising:

a plurality of vertically separated device levels, each level comprising an array of TFT EEPROMs, each TFT EEPROM comprising a channel, source and drain regions, and a charge storage region adjacent to the channel region;

a plurality of bit line columns in each device level, each bit line column contacting the source or the drain regions of the TFT EEPROMs;

a plurality of word line rows in each device level; and

at least one interlevel insulating layer located between the device levels;

wherein the plurality of vertically separated device levels comprise a monolithic plurality of vertically separated device levels.

2. The array of claim 1, wherein the charge storage region of each TFT EEPROM of the array of TFT EEPROMs comprises an ONO dielectric film or an insulating layer containing conductive nanocrystals.

3. The array of claim 1, wherein the charge storage region of each TFT BEPROM of the array of TFT EEPROMs comprises:

a tunnel dielectric above the channel of each TFT EEPROM;

a floating gate above the tunnel dielectric; and

a control gate dielectric above the floating gate.

4. The array of claim 1, further comprising:

sidewall spacers located adjacent to sidewalls of a control gate of each TFT EEPROM of the array of TFT EEPROMs, wherein the sidewall spacers have approximately the same height as each control gate of each TFT EEPROM; and

an intergate insulating layer which is located between the sidewall spacers above the source and drain regions of the TFT EEPROMs of the array of TFT EEPROMs in each device level, and wherein the intergate insulating layer has approximately the same height as the sidewall spacers.

5. The array of claim 4, wherein:

the plurality of word line rows are located on the sidewall spacers and on the intergate insulating layer in each device level; and

the word lines of the plurality of word line rows contact each control gate of each TFT EEPROM of the array of TFT EEPROMs through openings between the sidewall spacers.

6. The array of claim 5, wherein the plurality of bit line columns in each device level comprise rails which extend under the intergate insulating layer.

7. The array of claim 6, wherein:

the rails comprise suicide layers over doped semiconductor regions; and

the doped semiconductor regions comprise the source and drain regions of the TFT EEPROMs of the array of TFT EEPROMs in areas where the doped semiconductor regions are located adjacent to the channels of the TFT EEPROMs of the array of TFT EEPROMs.

8. The array of claim 1, wherein each TFT EEPROM of the array of TFT EEPROMs further comprises a control gate, and wherein the control gate of each TFT BEPROM comprises:

a first portion contacting the charge storage region; and

a second portion above the first portion;

wherein the first and the second portions comprise separately deposited layers.

9. The array of claim 1, further comprising word line contacts and bit line contacts which connect the word line rows and the bit line columns, respectively with peripheral circuits located in a semiconductor substrate below a first device level of the array.

10. The array of claim 9, wherein the word line and the bit line contacts extend between plural device layers.

11. The array of claim 1, wherein:

the array of TFT EEPROMs comprises a plurality of memory cells;

each memory cell of the plurality of memory cells comprises one TFT EEPROM of the array of TFT EEPROMs; and

each memory cell size per bit is about (2F²)/N, where F is a minimum feature size and N is a number of device layers in a third dimension and where N>

1.

12. The array of claim 1, wherein the charge storage region of each TFT EEPROM of the array of TFT EEPROMs comprises an ONO dielectric film.

13. The array of claim 1, wherein:

in at least one device level, the plurality of bit line columns are disposed on an opposite side of the channel of each TFT BEPROM of the array of TFT EEPROMs from the plurality of word line rows; and

the channel of each TFT BEPROM of the array of TFT EEPROMs comprises amorphous silicon or polysilicon.

14. The array of claim 13, wherein:

the plurality of bit line columns are disposed above the channel of each TFT BEPROM of the array of TFT EEPROMs; and

the plurality of word line rows are disposed below the channel of each TFT EEPROM of the array of TFT EEPROMs.

15. The array of claim 13, wherein:

the plurality of bit line columns are disposed below the channel of each TFT EEPROM of the array of TFT EEPROMs; and

the plurality of word line rows are disposed above the channel of each TFT EEPROM of the array of TFT EEPROMs.

16. The array of claim 1, wherein each word line row of the plurality of word line rows contacts control gates of a portion of the TFT EEPROMs of the array of TFT EEPROMs.

17. The array of claim 1, wherein each word line row of the plurality of word line rows acts as a control gate of a portion of the TFT EEPROMs of the array of TFT EEPROMs.

18. The array of claim 1, wherein:

the plurality of bit line columns extend substantially perpendicular to a source-channel-drain direction of the TFT EEPROMs of the array of TFT EEPROMs; and

the plurality of word line rows extend substantially parallel to the source-channel-drain direction of the TFT EEPROMs of the array of TFT EEPROMs.

19. The array of claim 1, wherein the channel of each TFT EEPROM of the array of TFT EEPROMs comprises amorphous silicon.

20. The array of claim 1, wherein the channel of each TFT EEPROM of the array of TFT EEPROMs comprises polysilicon.