Vertical compound semiconductor field effect transistor structure
First Claim
1. A semiconductor switching structure comprising:
- a depletion mode compound semiconductor sense FET device having a first doped gate region;
a depletion mode compound semiconductor main FET device having a second doped gate region;
a first source contact region coupled to the sense FET;
a second source contact region coupled to the main FET; and
a gate control structure coupled to the first and second doped gate regions, and wherein the sense FET device and the main FET device are configured as junction FET devices.
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Accused Products
Abstract
In one embodiment, a compound semiconductor vertical FET device (11) includes a first trench (29) formed in a body of semiconductor material (13), and a second trench (34) formed within the first trench (29) to define a channel region (61). A doped gate region (59) is then formed on the sidewalls and the bottom surface of the second trench (34). Source regions (26) are formed on opposite sides of the double trench structure (28). Localized gate contact regions (79) couple individual doped gate regions (59) together. Contacts (84,85,87) are then formed to the localized gate contact regions (79), the source regions (26), and an opposing surface (21) of the body of semiconductor material (13). The structure provides a compound semiconductor vertical FET device (11, 41, 711, 712, 811, 812) having enhanced blocking capability and improved switching performance.
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Citations
19 Claims
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1. A semiconductor switching structure comprising:
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a depletion mode compound semiconductor sense FET device having a first doped gate region; a depletion mode compound semiconductor main FET device having a second doped gate region; a first source contact region coupled to the sense FET; a second source contact region coupled to the main FET; and a gate control structure coupled to the first and second doped gate regions, and wherein the sense FET device and the main FET device are configured as junction FET devices. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. An integrated semiconductor switching structure comprising:
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a body of III–
V compound semiconductor material including a semiconductor substrate having a first dopant concentration and a first epitaxial layer formed on a surface of the semiconductor substrate, wherein the first epitaxial layer has a second dopant concentration less than the first dopant concentration;a depletion mode semiconductor sense FET device formed in the body of III–
V compound semiconductor material and having a first gate region;a depletion mode semiconductor main FET device formed in the body of III–
V compound semiconductor material and having a second gate region;a first source contact region coupled to the sense FET; a second source contact region coupled to the main FET; and a gate control structure coupled to the first and second gate regions. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 17, 18, 19)
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Specification