Vertical compound semiconductor field effect transistor structure

• US 7,129,544 B2
• Filed: 10/06/2004
• Issued: 10/31/2006
• Est. Priority Date: 07/18/2003
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Hadizad, Peyman
• Primary Examiner(s): Soward, Ida M.
• Application Number:
  US10/959,777
• Publication Number:
  US 20050056893A1
• Time in Patent Office: 755 Days
• Field of Search: 257/127, 257/135, 257/170, 257341-342, 257/348, 257/392, 257401-407
• US Class Current: 257/348
• CPC Class Codes: H01L 29/8083 Vertical transistors SIT H01L29/7722

Abstract

In one embodiment, a compound semiconductor vertical FET device (11) includes a first trench (29) formed in a body of semiconductor material (13), and a second trench (34) formed within the first trench (29) to define a channel region (61). A doped gate region (59) is then formed on the sidewalls and the bottom surface of the second trench (34). Source regions (26) are formed on opposite sides of the double trench structure (28). Localized gate contact regions (79) couple individual doped gate regions (59) together. Contacts (84,85,87) are then formed to the localized gate contact regions (79), the source regions (26), and an opposing surface (21) of the body of semiconductor material (13). The structure provides a compound semiconductor vertical FET device (11, 41, 711, 712, 811, 812) having enhanced blocking capability and improved switching performance.

Claims

1. A semiconductor switching structure comprising:

a depletion mode compound semiconductor sense FET device having a first doped gate region;

a depletion mode compound semiconductor main FET device having a second doped gate region;

a first source contact region coupled to the sense FET;

a second source contact region coupled to the main FET; and

a gate control structure coupled to the first and second doped gate regions, and wherein the sense FET device and the main FET device are configured as junction FET devices.

2. The structure of claim 1 wherein the sense FET device comprises a vertical GaAs n-channel depletion mode FET device.

3. The structure of claim 1 wherein the main FET device comprises a vertical GaAs n-channel depletion mode FET device.

4. The structure of claim 1 wherein the main FET device and the sense FET device are formed within a common body of semiconductor material.

5. The structure of claim 1 wherein the main FET device comprises a vertical double trench FET.

6. The structure of claim 1 wherein the sense FET device comprises a vertical double trench FET.

7. The structure of claim 1 wherein the main FET device comprises:

a body of semiconductor material comprising a first conductivity type, wherein the body of semiconductor material has an upper surface and a lower surface opposing the upper surface, wherein the lower surface provides a drain contact;

a first trench formed in the body of semiconductor material and extending from the upper surface, wherein the first trench has a first width, a first depth from the upper surface, first sidewalls, and a first bottom surface;

a second trench formed within the first trench, wherein the second trench has a second width, a second depth from the first surface, second sidewalls and a second bottom surface, wherein the first and second trenches form a first trench structure;

a first source region formed in the body of semiconductor material extending from the upper surface and spaced apart from the first trench; and

the second doped gate region formed in at least a portion of the second sidewalls and the second bottom surface, wherein the second doped gate region comprises a second conductivity type, and wherein the second doped gate region extends into the body of semiconductor material.

8. The structure of claim 1 wherein the sense FET device comprises:

a body of semiconductor material comprising a first conductivity type, wherein the body of semiconductor material has an upper surface and a lower surface opposing the upper surface, wherein the lower surface provides a drain contact;

a first trench formed in the body of semiconductor material and extending from the upper surface, wherein the first trench has a first width, a first depth from the upper surface, first sidewalls, and a first bottom surface;

a second trench formed within the first trench, wherein the second trench has a second width, a second depth from the first surface, second sidewalls and a second bottom surface, wherein the first and second trenches form a first trench structure;

a first source region formed in the body of semiconductor material extending from the upper surface and spaced apart from the first trench; and

the first doped gate region formed in at least a portion of the second sidewalls and the second bottom surface, wherein the first doped gate region comprises a second conductivity type, and wherein the first doped gate region extends into the body of semiconductor material.

9. An integrated semiconductor switching structure comprising:

a body of III–

V compound semiconductor material including a semiconductor substrate having a first dopant concentration and a first epitaxial layer formed on a surface of the semiconductor substrate, wherein the first epitaxial layer has a second dopant concentration less than the first dopant concentration;

a depletion mode semiconductor sense FET device formed in the body of III–

V compound semiconductor material and having a first gate region;

a depletion mode semiconductor main FET device formed in the body of III–

V compound semiconductor material and having a second gate region;

a first source contact region coupled to the sense FET;

a second source contact region coupled to the main FET; and

a gate control structure coupled to the first and second gate regions.

10. The structure of claim 9 wherein the depletion mode sense FET device comprises a vertical GaAs n-channel depletion mode FET device.

11. The structure of claim 9 wherein the depletion mode main FET device comprises a vertical GaAs n-channel depletion mode device.

12. The structure of claim 9 wherein the depletion mode main FET device comprises:

a first groove formed in the body of III–

V compound semiconductor material, wherein the first groove has first sidewalls and a first lower surface, and wherein the first groove extends from a first surface of the body of III–

V compound semiconductor material;

a second groove formed within the first groove, wherein the second groove has second sidewalls and a second lower surface;

the second doped gate region formed in the second lower surface and at least a portion of the second sidewalls and extending into the body of III–

V compound semiconductor material, wherein the second doped gate region comprises a second conductivity type;

a first source region of the first conductivity type formed in the first epitaxial layer adjacent to the first groove;

a source contact coupled to the first source region; and

drain contact formed on a second surface of the body of III–

V compound semiconductor material.

13. The structure of claim 12 further comprising a passivation layer formed over the first and second grooves.

14. The structure of claim 13 wherein the passivation layer comprises silicon nitride.

15. The structure of claim 13 further comprising a trench-fill layer formed over the passivation layer.

16. The structure of claim 15 wherein the trench-fill layer comprises one of a low temperature oxide, silicon nitride, and a spin on dielectric.

17. The structure of claim 9 wherein the depletion mode sense FET device comprises:

a first groove formed in the body of III–

V compound semiconductor material, wherein the first groove has first sidewalls and a first lower surface, and wherein the first groove extends from a first surface of the body of III–

V compound semiconductor material;

a second groove formed within the first groove, wherein the second groove has second sidewalls and a second lower surface;

the first doped gate region formed in the second lower surface and at least a portion of the second sidewalls and extending into the body of III–

V compound semiconductor material, wherein the first doped gate region comprises a second conductivity type;

a first source region of the first conductivity type formed in the first epitaxial layer adjacent to the first groove;

a source contact coupled to the first source region; and

a drain contact formed on a second surface of the body of III–

V compound semiconductor material.

18. The structure of claim 17 further comprising a passivation layer formed over the first and second grooves.

19. The structure of claim 18 further comprising a trench-fill layer formed over the passivation layer.