CMOS analog switch

• US 7,129,766 B2
• Filed: 07/27/2004
• Issued: 10/31/2006
• Est. Priority Date: 07/28/2003
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Steinhagen, Wolfgang
• Primary Examiner(s): TON, MY TRANG
• Application Number:
  US10/901,834
• Publication Number:
  US 20050046462A1
• Time in Patent Office: 826 Days
• Field of Search: 327/427, 327389-390, 327/404, 327/434
• US Class Current: 327/427
• CPC Class Codes: H03K 17/063 in field-effect transistor switches
• CPC Class Codes: H03K 2217/0018 Special modifications or use of the back gate voltage of a FET

Abstract

A CMOS analog switch is provided that can handle negative input polarity. The semiconductor substrate wherein the analog switch is formed has a substrate area of n-conductivity type. First and second p-channel transistors are formed in the n-conductivity substrate area and each have a gate, a source connected to the input terminal and a drain connected to the output terminal. The analog switch further has a comparator for comparing a voltage level at the input terminal with ground level, a switch driven by an output of the comparator to selectively connect the n-conductivity area with the signal input terminal for a positive input voltage level or to ground for a negative input voltage level, and control circuitry providing gate control signals for the first and second p-channel transistors. The inherent substrate diodes are effectively kept from becoming conductive.

Claims

1. A MOS circuit for switching an input signal, referenced to a ground, between a signal input terminal and a signal output terminal, comprising:

first and second p-channel transistors formed in an at least one n-conductivity type substrate area and each having a gate, a source connected to the signal input terminal and a drain connected to the signal output terminal;

a comparator for comparing a voltage level at the signal input terminal with ground;

a switch circuit driven by an output of said comparator to selectively connect the at least one n-conductivity type substrate area to the signal input terminal for a positive input voltage level or to the ground for a negative input voltage levels; and

a control circuitry providing gate control signals for the first and second p-channel transistors.

2. The MOS circuit of claim 1, wherein the gate control signals are derived from a clock signal.

3. The MOS circuit of claim 1, wherein the control circuitry comprises a pair of logic gates, each having a first input connected to a signal source, and each having a second input;

one of the second inputs being connected to the output of the comparator and another being connected to the output of the comparator through an inverting element.

4. The MOS circuit of claim 3, wherein the switch circuit comprises a first switching transistor with a source connected to the signal input terminal, a drain connected to the at least one n-conductivity type area and a gate connected to the control circuitry;

and a second switching transistor with a drain connected to ground, a source connected to the n-conductivity type area and a gate connected to the control circuitry.

5. The MOS circuit of claim 1, wherein the control circuitry has outputs that are capacitively coupled to the p-channel transistor gates.

6. The MOS circuit of claim 3, wherein the pair of logic gates comprises first and second NAND gates;

and further comprising a first capacitor connected to the output of the first NAND gate and also to the gate of the first p-channel transistor; and

a second capacitor connected to the output of the second NAND gate and also to the gate of the second p-channel transistor.

7. The MOS circuit of claim 4, wherein the control circuitry comprises a third switching transistor selectively connecting the gate of the first p-channel transistor to the signal input terminal;

and a fourth switching transistor selectively connecting the gate of the second p-channel transistor to the signal input terminal;

the third and fourth switching transistors being controlled in response to the signal source.

8. The MOS circuit of claim 1, wherein the control circuitry comprises a pair of logic gates, a first of the pair of logic gates having an input connected to the output of the comparator;

and a second of the pair of logic gates having an input connected to the output of the comparator through an inverting element.

9. A MOS circuit for switching an input signal, referenced to a ground, between a signal input terminal and a signal output terminal, comprising:

a first and second p-channel transistors formed in an at least one n-conductivity type substrate area and each having a gate, a source connected to the signal input terminal and a drain connected to the signal output terminals;

a comparator for comparing a voltage level at the signal input terminal with ground;

a first switch circuit driven by an output of said comparator to selectively connect the at least one n-conductivity type substrate area to the signal input terminal for a positive input voltage level or to ground for a negative input voltage level;

a control circuitry providing gate control signals for the first and second p-channel transistors;

wherein the control circuitry comprises a pair of logic gates, a first of the pair of logic gates having an input connected to the output of the comparator; and

a second of the pair of logic gates having an input connected to the output of the comparator through an inverting element;

wherein the pair of logic gates have outputs that are capacitively coupled to the p-channel transistor gates; and

a second switch circuit driven by a signal source to selectively connect the signal input terminal to each of the gates of the p-channel transistors.