Multilevel power amplifier architecture using multi-tap transformer

• US 7,129,784 B2
• Filed: 10/28/2004
• Issued: 10/31/2006
• Est. Priority Date: 10/28/2004
• Status: Expired due to Fees

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Castaneda, Jesus, Bhatti, Iqbal
• Primary Examiner(s): Pascal, Robert
• Assistant Examiner(s): NGUYEN, HIEU P
• Application Number:
  US10/975,240
• Publication Number:
  US 20060091958A1
• Time in Patent Office: 733 Days
• Field of Search: 330/295, 330/301, 330/276, 330/286
• US Class Current: 330/295
• CPC Class Codes: H03F 2200/108 A coil being added in the drain circuit of a FET amplifier stage, e.g. for noise reducing purposes
• CPC Class Codes: H03F 2200/372 Noise reduction and elimination in amplifier
• CPC Class Codes: H03F 2200/541 Transformer coupled at the output of an amplifier
• CPC Class Codes: H03F 2203/45731 the LC comprising a transformer
• CPC Class Codes: H03F 3/211 using a combination of several amplifiers H03F3/60 takes precedence
• CPC Class Codes: H03F 3/45188 Non-folded cascode stages
• CPC Class Codes: H03F 3/602 Combinations of several amplifiers

Abstract

A multi-level power amplifier architecture using a multi-tap transformer implemented on a single CMOS integrated circuit wireless communications device is described. By providing a multi-tap transformer for coupling a plurality of power amplifiers to a shared output impedance, such as an antenna, power transmission may be made at different levels while maintaining efficiency. With a multi-tap transformer having “N” taps featuring “N” different impedance levels, each tap may be connected to an amplifier cell which delivers power into the transformer at the tap for coupling to the output load. Any one of the “N” amplifier cells can be turned on at once along with any combination of the “N” amplifier cells.

Claims

1. A power amplifier system, comprising:

a plurality of power amplifiers comprising a first power amplifier and a second power amplifier, where each power amplifier receives an input signal and generates an output signal, and where any combination of the plurality of power amplifiers can be turned on at once;

a multi-tap transformer comprising a secondary winding and a primary winding formed in an integrated circuit, where the primary winding is operably coupled to a shared load impedance, and where the secondary winding comprises a plurality of input taps, where each tap is operably coupled to receive an output signal from one of the plurality of power amplifiers.

2. The power amplifier system of claim 1, where each power amplifier comprises:

an input transistor having a gate, a source, and a drain, wherein the gate is operably coupled to receive the input signal, and wherein the source is coupled to a first DC voltage potential;

an inductor operably coupled between a second DC voltage potential and the drain of the input transistor, where the drain of the input transistor is operably coupled to an input tap of the secondary winding to provide the output signal from the power amplifier to the multi-tap transformer.

3. The power amplifier system of claim 1, wherein an input signal to a power amplifier is coupled through a tap of the multi-tap transformer to the shared load impedance to provide on-chip impedance matching between the power amplifier and the shared load impedance.

4. The power amplifier system of claim 1, wherein the plurality of power amplifiers comprise a plurality of differential power amplifiers.

5. The power amplifier system of claim 1, wherein the plurality of power amplifiers comprise a plurality of single ended amplifiers.

6. The power amplifier system of claim 1, where the load impedance comprises an antenna.

7. The power amplifier system of claim 1, where the secondary winding comprises a first portion and a second portion formed on an integrated circuit layer, wherein a first differential output signal from the first power amplifier is operably coupled between a first node of the first portion and a first node of the second portion;

wherein a second differential output signal from the second power amplifier is operably coupled between a tap of the first portion and a tap of the second portion; and

wherein a second node of the first portion and a second node of the second portion is operably coupled to a reference potential.

8. The power amplifier system of claim 1, wherein the plurality of power amplifiers and the multi-tap transformer are integrated on a single integrated circuit.

9. An on-chip multi-tap transformer for coupling a plurality of power amplifiers to a shared output impedance, comprising:

a primary winding formed on a first layer of an integrated circuit and operably coupled to a shared output impedance;

a secondary winding formed on a second layer of the integrated circuit, said secondary winding comprising a plurality of input taps, where each input tap is operably coupled to receive an output signal from one of a plurality of power amplifiers such that each input tap provides a different impedance level for connecting the power amplifier coupled to the input tap through to the shared impedance, and where any combination of the plurality of power amplifiers can be turned on at once.

10. The multi-tap transformer of claim 9, where the shared output impedance comprises an antenna.

11. The multi-tap transformer of claim 9, where the plurality of input taps comprises a first set of input taps for receiving a first differential input signal and a second set of input taps for receiving a second differential input signal.

12. The multi-tap transformer of claim 9, where the plurality of input taps comprises a reference input tap coupled to a reference potential, a first input tap for receiving a first single-ended input signal and a second input tap for receiving a second single-ended input signal.

13. The multi-tap transformer of claim 9, where the secondary winding comprises a common node, a first portion and a second portion, where each portion has one node, a first tap and a second tap.

14. The multi-tap transformer of claim 13, where the common node is operably coupled to a ground reference potential, the nodes from the first and second portions are operably coupled to receive a first differential input signal, the first taps of the first and second portions are operably coupled to receive a second differential input signal, and the second taps of the first and second portions are operably coupled to receive a third differential input signal.

15. The multi-tap transformer of claim 9, where the secondary winding has a generally octagonal geometric shape.

16. The multi-tap transformer of claim 9, where the secondary winding comprises a common node, a first portion and a second portion, where each portion has one node and multiple taps.

17. A method for efficiently delivering power to an output impedance through an on-chip multiple tap transformer, comprising:

connecting a multiple tap transformer output to an output impedance;

selectively coupling a plurality of power amplifiers to a corresponding plurality of multiple tap transformer inputs, where each multiple tap transformer input provides a predetermined load impedance for the power amplifier that is coupled to said multiple tap transformer input, thereby providing a multiple tap transformer having a variable load impedance, depending on which power amplifiers are turned on.

18. The method of claim 17 implemented on a single CMOS integrated circuit wireless communications device.