Method and architecture for an improved CMOS color image sensor

• US 7,129,978 B1
• Filed: 07/13/1999
• Issued: 10/31/2006
• Est. Priority Date: 07/13/1998
• Status: Expired due to Term

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Zoran Corporation (Qualcomm, Inc.)
• Inventors: Wiedemann, Rudolf A., Brehmer, Kevin E., Erdogan, Ozan E.
• Primary Examiner(s): HO, TUAN V
• Application Number:
  US09/352,494
• Time in Patent Office: 2,667 Days
• Field of Search: 348/294, 348/300, 348/302, 348/308, 348/207.99, 348/222.1, 348/223.1, 348/229.1, 348/230.1, 348/241, 348/254, 250/208.1
• US Class Current: 348/308
• CPC Class Codes: H04N 25/443 by reading pixels from selected 2D regions of the array, e.g. for windowing or digital zooming
• CPC Class Codes: H04N 25/445 by skipping some contiguous pixels within the read portion of the array
• CPC Class Codes: H04N 25/76 Addressed sensors, e.g. MOS or CMOS sensors

Abstract

According to the principles of this invention, an improved CMOS image sensor is disclosed. The improved CMOS image sensor comprises a pair of controllable column and row decoders, a signal conditioning circuit and a pixel processor in addition to an array of photo sensors. With the pair of controllable column and row decoders, photo sensors can selectively and dynamically accessed to improve signal throughput for applications that do not require the full set of signals from the array of photo sensors. The digitized signals from the selected photo sensors can be processed in the pixel processor for auto focus, pixel signals decimation and interpolation, data conversation and compression. Consequently, the design complexity of an overall imaging system using the disclosed CMOS image sensor is considerably reduced and the performance thereof is substantially increased.

Claims

1. A method for facilitating high signal throughput of an improved CMOS image sensor comprising a plurality of photo sensors configured in a two-dimensional area, said method comprising:

reading out charge signals from said plurality of photo sensors row by row in parallel to respective column buses;

said column buses coupled to a double sampling circuit and a programmable gain amplifier;

producing pixel signals by digitizing said charge signals with an analog-to-digital converter;

conditioning said charge signals in said programmable gain amplifier in accordance with said double sampling circuit before said charge signals are digitized to produce the pixel signals; and

processing said pixel signals in a pixel processor to produce a desired result.

2. The method as recited in claim 1 wherein said pixel processor, said double sampling circuit and said programmable gain amplifier are monolithically integrated with said plurality of photo sensors of the CMOS image sensor.

3. The method as recited in claim 1 wherein said conditioning said charge signals comprises:

deriving a measurement difference of each of said charge signals with a reference in said double sampling circuit; and

adjusting said each of said charge signals with respect to said measurement difference said programmable gain amplifier.

4. The method as recited in claim 1 wherein said desired result is a compressed format of said pixel signals and wherein said processing said pixel signals in a pixel processor comprises compressing said pixel signals according to a commonly used compression standard.

5. The method as recited in claim 4 wherein the commonly used compression standard is selected from a group consisting of Graphic Interchange Format (GIF), JPEG (Joint Photographic Experts Group) and MPEG (Moving Picture Experts Group) supported by a World Wide Web protocol.

6. The method as recited in claim 1 wherein said desired result is a gray-scale intensity image and wherein said processing said pixel signals in a pixel processor comprises converting said pixel signals respectively to intensity data according to a predefined conversion standard.

7. An architecture for facilitating high signal throughput of an improved CMOS image sensor comprising a plurality of photo sensors configured in a two-dimensional area, said architecture comprising:

a pair of column address and row address decoders providing address signals to address each of the plurality of photo sensors;

a number of signal conditioning circuits, said signal conditioning circuits comprising a correlated double sampling circuit and a programmable gain amplifier, said signal conditioning circuits coupled to a column data bus for receiving charge signals read out from said photo sensors when said photo sensors are addressed by said address signals;

a number of analog-to-digital converters, each respectively coupled to one of said conditioning circuits and digitizing said charge signals in parallel to produce pixel signals; and

a pixel processor for receiving said pixel signals from said analog-to-digital converters, wherein said pixel signals are processed to produce a desired result.

8. The architecture as recited in claim 7 wherein said correlated double sampling circuit derives a measurement difference of each of said charge signals with a reference.

9. The architecture as recited in claim 8 wherein said programmable gain amplifier receives said measurement difference and adjusts said each of said charge signals with respect to said measurement difference.

10. The architecture as recited in claim 8 wherein each of the signal conditioning circuits produces a signal that indicates an optimum exposure time.

11. The architecture as recited in claim 10 wherein said correlated double sampling circuit and said programmable gain amplifier together derive a measurement difference of each of said charge signals with a reference;

and calculate said optimum exposure time from said measurement difference.

12. The architecture as recited in claim 7 further comprises a memory storing instructions, said memory coupled to said pixel processor that executes said instructions from said memory to achieve said desired result.

13. The architecture as recited in claim 12 wherein said instructions cause said pixel processor to compress said pixel signals according to a commonly used compression standard.

14. The architecture as recited in claim 13 wherein the commonly used compression standard is selected from a group consisting of GIF_(Graphic Interchange Format), JPEG (Joint Photographic Experts Group) and MPEG (Moving Picture Experts Group) supported by a World Wide Web protocol.

15. The architecture as recited in claim 12 wherein said instructions cause said pixel processor to convert said pixel signals respectively to intensity data according to a predefined conversion standard.

16. The architecture as recited in claim 7 wherein said pixel processor is monolithically integrated with said plurality of photo sensors.

17. The architecture as recited in claim 7 wherein said pixel processor, said correlated double sampling circuit and said programmable gain amplifier are monolithically integrated with said plurality of photo sensors.

18. An architecture for facilitating high signal throughput of an improved CMOS image sensor comprising a plurality of photo sensors configured in a two-dimensional area;

said architecture comprising;

a pair of column address and row address decoders providing address signals to address each of the plurality of photo sensors;

a number of signal conditioning circuits, each coupled to a column data bus for receiving charge signals read out from said photo sensors when said photo sensors are addressed by said address signals;

a number of analog-to-digital converters, each respectively coupled to one of said conditioning circuits and digitizing said charge signals in parallel to produce pixel signals;

a pixel processor for receiving said pixel signals from said analog-to-digital converters;

a memory loaded with one or more instructions accessed by the pixel processor; and

wherein said pixel signals are processed to produce a desired result.

19. The architecture as recited in claim 18 wherein each of the signal conditioning circuits comprises a correlated doubled sampling circuit and a programmable gain amplifier.

20. The architecture as recited in claim 19 wherein said correlated double sampling circuit derives a measurement difference of each of said charge signals with a reference.

21. The architecture as recited in claim 20 wherein said programmable gain amplifier receives said measurement difference and adjusts said each of said charge signals with respect to said measurement difference.

22. The architecture as recited in claim 20 wherein each of the signal conditioning circuits produces a signal that indicates an optimum exposure time.

23. The architecture as recited in claim 22 wherein said correlated double sampling circuit and said programmable gain amplifier together derive a measurement difference of each of said charge signals with a reference;

and calculate said optimum exposure time from said measurement difference.

24. The architecture as recited in claim 19 wherein said pixel processor, said correlated double sampling circuit and said programmable gain amplifier are monolithically integrated with said plurality of photo sensors.

25. The architecture as recited in claim 18 wherein said instructions cause said pixel processor to compress said pixel signals according to a commonly used compression standard.

26. The architecture as recited in claim 25 wherein the commonly used compression standard is selected from a group consisting of GIF (Graphic Interchange Format), JPEG (Joint Photographic Experts Group) and MPEG (Moving Picture Experts Group) supported by a World Wide Web protocol.

27. The architecture as recited in claim 18 wherein said instructions cause said pixel processor to convert said pixel signals respectively to intensity data according to a predefined conversion standard.

28. The architecture as recited in claim 18 wherein said pixel processor is monolithically integrated with said plurality of photo sensors.