Chip-to-chip communication system using an ac-coupled bus and devices employed in same

• US 7,130,944 B2
• Filed: 12/23/2004
• Issued: 10/31/2006
• Est. Priority Date: 09/17/1999
• Status: Expired due to Fees

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Barth, Richard M., Garlepp, Bruno W., Liaw, Haw-Jyh, Moncayo, Alfredo, Donnelly, Kevin, Perino, Donald V.
• Primary Examiner(s): Myers, Paul R.
• Application Number:
  US11/021,207
• Publication Number:
  US 20050135182A1
• Time in Patent Office: 677 Days
• Field of Search: 710/110, 710/305, 325/275
• US Class Current: 710/110
• CPC Class Codes: G06F 13/423 with synchronous protocol
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 23/48 Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/12032 Schottky diode
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

A chip-to-chip communication system and interface technique. A master and at least two devices are interconnected with a signal line of a high speed bus. A capacitive coupling element, for example a diode, is employed to capacitively couple the interface of the device to the signal line. By employing the capacitive coupling element, along with a suitable signaling technique which supports capacitive information transfer, high speed rates of information transfer between the master and device over the signal line are achieved.

Claims

1. A system comprising:

a controller device;

a substrate;

a signal line disposed in the substrate, the signal line to be coupled to the controller device;

a first electrode coupled to the signal line;

an integrated circuit memory device; and

a second electrode coupled to the integrated circuit memory device, wherein a dielectric material separates the first electrode from the second electrode to form a capacitive coupling element,

wherein the integrated circuit memory device is disposed in a housing and the second electrode is disposed on the housing.

2. The system of claim 1, wherein the first electrode and the second electrode are plates.

3. The system of claim 1, wherein the dielectric material includes an elastomer material.

4. The system of claim 1, wherein the first electrode includes a snap-in coupling socket disposed on the substrate.

5. The system of claim 4, wherein the second electrode is a snap-in coupler to be inserted into the snap-in coupling socket.

6. The system of claim 4, wherein the controller device is a memory controller, wherein the substrate is a printed circuit board and the integrated circuit memory device is a dynamic random access memory device.

7. The system of claim 1, wherein the controller device transmits a signal to the integrated circuit memory device, wherein the signal is encoded to avoid a predetermined number of like consecutive symbols.

8. The system of claim 1, wherein the controller device transmits a signal to the integrated circuit memory device, wherein the signal is a phase modulated signal.

9. The system of claim 1, wherein the controller device transmits a signal to the integrated circuit memory device, wherein the signal is a delay modulated signal.

10. The system of claim 1, wherein the controller device transmits a signal to the integrated circuit memory device, wherein the signal is a transition detection encoded signal.

11. A system comprising:

a memory controller;

a memory module having a substrate;

a signal line disposed in the substrate, the signal line to be coupled to the memory controller device;

a first electrode coupled to the signal line, the first electrode including a snap-in socket disposed on the substrate; and

an integrated circuit memory device including a second electrode having a snap-in coupler to be inserted into the snap-in socket;

wherein the integrated circuit memory device receives a signal transmitted by the memory controller when the snap-in coupler is inserted into the snap-in socket, wherein the signal is transmitted by the memory controller in accordance with a capacitive coupling transfer characteristic.

12. The system of claim 11, wherein a dielectric material separates the first electrode from the second electrode to form a capacitive coupling element.

13. The system of claim 12, wherein the dielectric material includes an elastomer material.

14. The system of claim 12, wherein the integrated circuit memory device has an input capacitance and the capacitive coupling element is configured to provide a reduced effective capacitance to the signal line that reduces a signal loss of the signal on the signal line.

15. The system of claim 11, wherein the integrated circuit memory device is disposed in a housing and the second electrode is disposed on the housing.

16. The system of claim 11, wherein the substrate is a printed circuit board and the integrated circuit memory device is a dynamic random access memory device.

17. The system of claim 11, wherein the signal is encoded to avoid a predetermined number of like consecutive symbols.

18. The system of claim 11, wherein the signal is a phase modulated signal.

19. The system of claim 11, wherein the signal is a delay modulated signal.

20. The system of claim 11, wherein the signal is a transition detection encoded signal.

21. The system of claim 11, wherein the integrated circuit memory device includes:

a circuit to provide a transition encoded output signal; and

a circuit to detect a transition encoded input signal.

22. A method of operation in a memory system including a memory controller coupled to an integrated circuit memory device by a signal line disposed on a substrate, the method comprising:

encoding a data signal by the memory controller;

transmitting, by the memory controller, the data signal via a first plate electrode coupled to the signal line;

receiving the data signal, by the integrated circuit memory device, via a second plate electrode coupled to a housing of the integrated circuit memory device, wherein the first plate electrode and the second plate electrode form a capacitive coupling element; and

decoding the data signal by the integrated circuit memory device.

23. The method of claim 22, further comprising:

providing the data signal with transition encoding; and

detecting transition encoding in the data signal.

24. The method of claim 22, wherein the data signal is encoded to avoid a predetermined number of like data bits.

25. The method of claim 22, wherein the data signal is a phase modulated signal.

26. The method of claim 22, wherein the data signal is a delay modulated signals.