Serial interface to flash-memory chip using PCI-express-like packets and packed data for partial-page writes
First Claim
1. A serial flash-memory chip comprising:
- a flash-memory array of electrically-erasable programmable read-only memory (EEPROM) cells;
row and column decoders for selecting EEPROM cells in the flash-memory array for reading, writing, or erasing in response to a flash address;
a serial-bus interface to a serial bus connected to pins of the serial flash-memory chip, for transmitting and receiving serial data over the serial bus;
a serial engine, coupled to the serial-bus interface, for converting serial data from the serial bus to parallel data;
an internal controller, coupled to the serial engine, for responding to flash commands sent over the serial bus in request packets, and for generating completion packets that are sent over the serial bus in response to the flash commands; and
data buffers, coupled between the flash-memory array and the internal controller, for buffering data read from the EEPROM cells in response to the internal controller decoding a read flash command in a read-request packet, the data being loaded into a data payload of a completion packet;
wherein the internal controller programs data into the EEPROM cells through the data buffers in response to a program flash command in a write-request packet received over the serial bus,whereby the serial flash-memory chip has a serial-packet interface for commands, address, and data.
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Accused Products
Abstract
A serial flash-memory chip has a serial-bus interface to an external controller. A flash-memory block in the serial flash-memory chip can be read by the external controller sending a read-request packet over the serial bus to the serial flash-memory chip, which reads the flash memory and sends the data back in a data-payload field in a completion packet. Data in a write-request packet is written to the flash memory, and a message packet sent back over the serial bus. The serial bus can be a Peripheral Component Interconnect (PCI) Express bus with bi-directional pairs of differential lines. Packets have modified-PCI-Express headers that define the packet type and data-payload length. Vendor-defined packets can send flash commands such as reset, erase, or responses after operations such as program or erase. A serial engine and microcontroller or state machine are on the serial flash-memory chip.
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Citations
21 Claims
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1. A serial flash-memory chip comprising:
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a flash-memory array of electrically-erasable programmable read-only memory (EEPROM) cells; row and column decoders for selecting EEPROM cells in the flash-memory array for reading, writing, or erasing in response to a flash address; a serial-bus interface to a serial bus connected to pins of the serial flash-memory chip, for transmitting and receiving serial data over the serial bus; a serial engine, coupled to the serial-bus interface, for converting serial data from the serial bus to parallel data; an internal controller, coupled to the serial engine, for responding to flash commands sent over the serial bus in request packets, and for generating completion packets that are sent over the serial bus in response to the flash commands; and data buffers, coupled between the flash-memory array and the internal controller, for buffering data read from the EEPROM cells in response to the internal controller decoding a read flash command in a read-request packet, the data being loaded into a data payload of a completion packet; wherein the internal controller programs data into the EEPROM cells through the data buffers in response to a program flash command in a write-request packet received over the serial bus, whereby the serial flash-memory chip has a serial-packet interface for commands, address, and data. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A flash-memory chip with a serial-packet interface comprising:
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a serial-bus interface to an external serial bus that transfers serial packets that include a memory-read-request packet, a memory-write-request packet, a configuration-read-request packet, and an input message packet input to the flash-memory chip, and a completion packet and an output message packet output from the flash-memory chip; flash memory means for storing data in non-volatile flash-memory cells; controller means, coupled to the flash memory means and to the serial-bus interface, for performing operations identified by commands in the serial packets, the operations including; reading data from the flash memory means at a flash address included in a header for the memory-read-request packet to generate a data payload for the completion packet; writing data to the flash memory means at the flash address included in a header for the memory-write-request packet, the data being sent in a data payload in the memory-write-request packet; reading a status from a configuration register identified by a header in the configuration-read-request packet to generate a data payload for the completion packet; erasing a block of memory in the flash memory means in response to an erase indicator in a header in the input message packet and generating the output message packet once erasing is completed; and resetting the flash-memory chip in response to a reset indicator in a header in the input message packet, whereby operations are performed by the flash-memory chip in response to commands in serial packets received over the external serial bus include generation of completion packets with the data payload read from the flash memory means. - View Dependent Claims (15, 16, 17)
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18. A Peripheral Component Interconnect (PCI) Express flash-memory chip comprising on a single semiconductor substrate:
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a flash memory array of non-volatile electrically-erasable programmable read-only memory (EEPROM) cells; address decoders, receiving a flash address, the address decoders selecting a subset of the EEPROM cells for reading, writing, or erasing; a high-voltage generator for generating elevated voltages above a power-supply voltage for programming and erasing the EEPROM cells; data buffers for storing data being written to the EEPROM cells; a command register receiving a flash command; control logic, responsive to the flash command in the command register, for controlling reading, writing, and erasing of the EEPROM cells; a serial interface to external pins of the PCI Express flash-memory chip that connect to an external serial bus, the serial interface having a physical layer; wherein the external serial bus is a PCI Express serial bus having differential data lines that carry data serially; a controller, connected between the serial interface and the command register and data buffers, the controller comprising; a data-link layer that encapsulates transaction-layer packets for transmission over the external serial bus after framing by the physical layer; a transaction layer that generates headers to attach to data payloads to generate the transaction-layer packets; read operation means, responsive to a memory-read-request packet received over the external serial bus having a header with the flash address, for sending a read command to the command register and sending the flash address to the address decoders, and transferring data read from the EEPROM cells from the data buffers to the transaction layer as a data payload, the transaction layer attaching the data payload to a header to generate a completion packet with the read data, the completion packet being sent over the external serial bus as a response to the memory-read-request packet; program operation means, responsive to a memory-write-request packet received over the external serial bus having a header with the flash address, for sending a write command to the command register and sending the flash address to the address decoders, and transferring data write from a data payload of the memory-write-request packet to the data buffers for writing to the EEPROM cells; erase operation means, responsive to a message packet received over the external serial bus having a header with an erase indicator, for sending an erase command to the command register, and generating a message packet for transmission over the external serial bus once the EEPROM cells have been erased; and reset operation means, responsive to a message packet received over the external serial bus having a header with a reset indicator, for sending a reset command to the control logic to reset the control logic and to reset the controller, whereby operations indicated by commands in serial packets received over the external serial bus are executed and data is returned in data payloads of serial packets. - View Dependent Claims (19, 20, 21)
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Specification