Apparatus and method for efficient decoder normalization

• US 7,131,054 B2
• Filed: 09/17/2001
• Issued: 10/31/2006
• Est. Priority Date: 09/17/2001
• Status: Expired due to Term

• Current Assignee: ARRIS Enterprises LLC (CommScope Holding Company, Inc.)
• Original Assignee: Digeo Incorporated (CommScope Holding Company, Inc.)
• Inventors: Shah, Manish, Greenberg, Mark
• Primary Examiner(s): Baker, Stephen M.
• Application Number:
  US09/955,558
• Publication Number:
  US 20030135814A1
• Time in Patent Office: 1,870 Days
• Field of Search: 714/795, 714/796, 375/341
• US Class Current: 714/795
• CPC Class Codes: H03M 13/2707 Simple row-column interleaver, i.e. pure block interleaving
• CPC Class Codes: H03M 13/41 using the Viterbi algorithm or Viterbi processors
• CPC Class Codes: H03M 13/4107 implementing add, compare, select [ACS] operations
• CPC Class Codes: H03M 13/6362 by puncturing
• CPC Class Codes: H03M 13/6583 Normalization other than scaling, e.g. by subtraction
• CPC Class Codes: H04N 21/4263 involving specific tuning arrangements, e.g. two tuners
• CPC Class Codes: H04N 21/4382 Demodulation or channel decoding, e.g. QPSK demodulation analog front ends or means for connecting modulators, demodulators or transceivers to a transmission line H04L27/0002

Abstract

An apparatus and method are described for normalizing a plurality of state metric values stored in a plurality of accumulators. In one embodiment, normalization logic monitors the each of the state metric values. When all of the values are above a predetermined threshold, the normalization logic subtracts a normalization amount from each of the state metric values. In one embodiment, the normalization amount is incorporated into branch metric calculations at one or more branch metric units. In addition, in one embodiment, different normalization amounts are employed based on the state metric values.

Claims

1. In a decoder having one or more branch metric units for calculating branch metric values, a method for performing normalization comprising:

if a specified normalization condition is met, subtracting a normalization amount from a branch metric value at each of said branch metric units to produce a normalized branch metric value; and

if a second specified normalization condition is met, subtracting a second normalization amount from branch metric calculations performed by each of said one or more branch metric units to produced a second normalized branch metric value.

2. The method as in claim 1 wherein said specified normalization condition is that a plurality of state metrics are above a threshold value.

3. The method as in claim 1 wherein said branch metric calculations are Viterbi branch metric calculations.

4. The method as in claim 1 wherein said second specified normalization condition is that a plurality of state metrics are above a second threshold value.

5. The method as in claim 1 further comprising adding said normalized branch metric value to a plurality of stored state metric values.

6. The method as in claim 5 wherein said state metric values are stored in a plurality of accumulators.

7. An apparatus comprising:

normalization logic to generate a normalization signal responsive to a specified normalization condition; and

a branch metric unit to subtract a normalization amount from a branch metric value responsive to said normalization signal, wherein said normalization logic generates a second normalization signal responsive to a second apecified normalization condition, and wherein said branch metric unit subtracts a second normalization amount from said branch metric value responsive to said second normalization signal.

8. The apparatus as in claim 7 wherein said specified normalization condition is that a plurality of state metric values are above a threshold value.

9. The apparatus as in claim 7 wherein said branch metric value is a Viterbi branch metric value.

10. The apparatus as in claim 7 wherein said second specified normalization condition is that a plurality of state metric values are above a second threshold value.

11. The apparatus as in claim 7 further comprising:

an adder to add said normalized branch metric value to a plurality of stored state metric values.

12. The apparatus as in claim 11 further comprising:

a plurality of accumulators for storing said state metric values.

13. A machine-readable medium having code stored thereon which defines an integrated circuit (IC), said IC comprising:

normalization logic to generate a normalization signal responsive to a specified normalization condition; and

a branch metric unit to subtract a normalization amount from a branch metric value responsive to said normalization signal, wherein said normalization logic generates a second normalization signal responsive to a second specified normalization condition, and wherein said branch metric unit subtracts a second normalization amount from said branch metric value responsive to said second normalization signal.

14. The machine-readable medium as in claim 13 wherein said specified normalization condition is that a plurality of state metric values are above a threshold value.

15. The machine-readable medium as in claim 13 wherein said branch metric value is a Viterbi branch metric value.

16. The machine-readable medium as in claim 13 wherein said second specified normalization condition is that a plurality of state metric values are above a second threshold value.

17. The machine-readable medium as in claim 13 wherein said IC further comprises:

an adder to add said normalized branch metric value to a plurality of stored state metric values.

18. The machine-readable medium as in claim 17 wherein said IC further comprises:

a plurality of accumulators for storing said state metric values.