Delay distribution calculation method, circuit evaluation method and false path extraction method
First Claim
1. A method for evaluating an integrated circuit to be designed, comprising:
- a first step of producing an equivalent circuit that does not include a path corresponding to a false path, based on circuit information indicating connection between components in the integrated circuit; and
a second step of evaluating the integrated circuit by using the equivalent circuit produced in the first step,wherein false path information indicating the false path is used, and the false path information represents the false path by two vertices on a graph representing the integrated circuit,wherein the first step includes the steps ofextracting a first partial circuit provided with a first vertex as an input and a second vertex as an output, the first vertex and the second vertex are two vertices representing the false path,making a copy of the first partial circuit as a second partial circuit, andmodifying connection of the first and second partial circuits and another circuit such that there exists no path from the first vertex toward the second vertex.
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Abstract
Delay distribution in an integrated circuit is calculated while taking into account a correlation of performance between interconnects or elements in the integrated circuit, thereby improving estimation accuracy. Circuit information, performance distribution information of the interconnects or elements in the integrated circuit, and correlation information of performance between the interconnects or elements are input. A vertex is selected for calculation, and a correlation between delay distribution at the selected vertex and delay distribution in a partial circuit including the selected vertex is calculated based on the performance distribution information and the correlation information.
21 Citations
3 Claims
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1. A method for evaluating an integrated circuit to be designed, comprising:
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a first step of producing an equivalent circuit that does not include a path corresponding to a false path, based on circuit information indicating connection between components in the integrated circuit; and a second step of evaluating the integrated circuit by using the equivalent circuit produced in the first step, wherein false path information indicating the false path is used, and the false path information represents the false path by two vertices on a graph representing the integrated circuit, wherein the first step includes the steps of extracting a first partial circuit provided with a first vertex as an input and a second vertex as an output, the first vertex and the second vertex are two vertices representing the false path, making a copy of the first partial circuit as a second partial circuit, and modifying connection of the first and second partial circuits and another circuit such that there exists no path from the first vertex toward the second vertex. - View Dependent Claims (2, 3)
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Specification
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- Resources
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Current AssigneeSocionext Inc.
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Original AssigneeMatsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
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InventorsFukui, Masahiro, Tanaka, Masakazu, Tsukiyama, Shuji
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Primary Examiner(s)Dinh, Paul
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Application NumberUS10/739,309Publication NumberTime in Patent Office1,047 DaysField of Search716/2, 716 4- 6, 716/18, 703/19US Class Current716/103CPC Class CodesG05B 19/0421 Multiprocessor systemG06F 2111/08 Probabilistic or stochastic...G06F 2119/12 Timing analysis or timing o...G06F 30/00 Computer-aided design [CAD]G06F 30/3312 Timing analysisG06F 30/3315 using static timing analysi...
