Logic generation for multiple memory functions

• US 7,131,097 B1
• Filed: 09/24/2002
• Issued: 10/31/2006
• Est. Priority Date: 09/24/2002
• Status: Expired due to Fees

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Schlacter, Guy R
• Primary Examiner(s): THOMPSON, ANNETTE M
• Application Number:
  US10/253,379
• Time in Patent Office: 1,498 Days
• Field of Search: 716/16, 716/1, 716/8, 716/18
• US Class Current: 716/102
• CPC Class Codes: G06F 30/30 Circuit design

Abstract

Methods are provided for helping to automate the design of electronic circuitry in which multiple memory functions are provided by common physical memory. Interactive computer screens prompt the user to enter information about the multiple memory functions that the user desires. The data thus entered by the user is then reformatted for use as specific values of parameters in a parameterized function that can provide the required circuit design when its parameters are thus supplied with specific values.

Claims

1. A method of collecting data for use in providing a circuit design in which multiple memory functions share common physical memory circuitry comprising:

allowing a user to input data specifying type information for each of the multiple memory functions, the memory functions including at least one of dual-port random access memory and first-in/first-out memory, wherein the type information relates to a provision of optional registers for data from a memory function for pipelining, wherein the type information relates to provision of a common read port and a common write port for the multiple memory functions, and further wherein the type information relates to independently operating memory functions;

allowing the user to input data specifying size information for each of the multiple memory functions; and

allowing the user to input data specifying operating speed information for each of the multiple memory functions.

2. The method defined in claim 1 wherein the memory functions further include true dual-port random access memory and single-port random access memory.

3. The method defined in claim 1 wherein the size information comprises input port width and output port width.

4. The method defined in claim 3 wherein the size information further comprises memory depth.

5. The method defined in claim 1 wherein the operating speed information comprises input port speed and output port speed.

6. The method defined in claim 1 wherein the type information is selected in part from the group consisting of provision of a read request signal and provision of a read acknowledge signal.

7. A method of collecting data for use in providing a circuit design in which multiple memory functions share common physical memory circuitry comprising:

allowing a user to input data specifying type information for each of the multiple memory functions, the memory functions including at least one of dual-port random access memory and first-in/first-out memory, wherein the type information relates to a provision of optional registers for data from a memory function for pipelining, wherein the type information relates to provision of a common read port and a common write port for the multiple memory functions, and further wherein the type information relates to provision of a byte enable port allowing the user to specify the width of a byte;

allowing the user to input data specifying size information for each of the multiple memory functions; and

allowing the user to input data specifying operating speed information for each of the multiple memory functions.

8. A method of collecting data for use in providing a circuit design in which multiple memory functions share common physical memory circuitry comprising:

allowing a user to input data specifying type information for each of the multiple memory functions, the memory functions including at least one of dual-port random access memory and first-in/first-out memory, wherein the type information relates to a provision of optional registers for data from a memory function for pipelining, wherein the type information relates to provision of a common read port and a common write port for the multiple memory functions, and further wherein the type information relates to provision of a clear signal for the multiple memory functions;

allowing the user to input data specifying size information for each of the multiple memory functions; and

allowing the user to input data specifying operating speed information for each of the multiple memory functions.