Test structure for detecting defect size in a semiconductor device and test method using same

• US 7,132,684 B2
• Filed: 04/29/2004
• Issued: 11/07/2006
• Est. Priority Date: 06/27/2003
• Status: Expired due to Fees

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Jong-hyun
• Primary Examiner(s): Zarneke, David A.
• Application Number:
  US10/834,071
• Publication Number:
  US 20040262604A1
• Time in Patent Office: 922 Days
• Field of Search: 257/48
• US Class Current: 257/48
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633

Abstract

A test structure and method for testing a semiconductor device are provided. The test structure including a first test pattern having a plurality of electrically separated metal patterns, a plurality of metal vias formed in opposite end portions of the respective metal patterns, and a second test pattern connected to the first test pattern through the metal vias. By using this structure, the presence, nature, and size of a metal failure can be detected by analyzing a resistance arising from the application of a test voltage to the first test pattern.

Claims

1. A test structure for a semiconductor device, the test structure comprising:

a first test pattern including a plurality of electrically separated metal patterns;

a plurality of metal vias formed proximate first and second end portions of each one of the plurality of metal patterns forming the first test pattern; and

a second test pattern electrically connected in parallel to the first test pattern by the plurality of metal vias,

such that a test voltage applied to the first test pattern indicates a resistance that varies in accordance with the presence and nature of a metal failure;

wherein the second test pattern comprises an element selected from a group consisting of tungsten, aluminum, copper, or an alloy of these materials.

2. The test structure of claim 1, wherein the metal patterns forming the first test pattern comprise an input pad receiving the test voltage and an output pad discharging the applied test voltage.

3. The test structure of claim 1, wherein the metal patterns forming the first test pattern are comprised of one selected from the group consisting of aluminum, copper, or an alloy of these materials.

4. The test structure of claim 1, wherein the metal vias are formed from at least one of tungsten and copper.

5. A method of testing a semiconductor device using a test structure, wherein the test structure comprises;

a first test pattern including a plurality of electrically separated metal patterns;

a plurality of metal vias formed proximate first and second end portions of each one of the plurality of metal patterns forming the first test pattern; and

a second test pattern electrically connected in parallel to the first test pattern by the plurality of metal vias,

method comprising;

applying a test voltage to the first test pattern; and

,

detecting the presence of a metal failure in relation to a resistance indicated upon application of the test voltage;

wherein the second test pattern comprises an element selected from a group consisting of tungsten, aluminum, copper, or an alloy of these materials.

6. The test method of claim 5, wherein the test structure further comprises an input pad connected to one side of the first test pattern and receiving the test voltage, and an output pad connected to an opposite side of the first test pattern and discharging the test voltage, such that an electrical current flows from the input pad to the output pad through a combination of the first test pattern, the metal vias, and the second test pattern.

7. The test method of claim 6, wherein the nature of the metal failure is additionally indicated by the resistance arising from application of the test voltage to the input pad.

8. The test method of claim 5, wherein the nature of the metal failure comprises either a short or an open connection.

9. The test method of claim 8, wherein a number of either shorted or open connections is indicated by the resistance arising from application of the test voltage to the input pad.

10. The test method of claim 5, wherein a normal resistance R_NOR indicates the absence of a metal failure, R_NOR being defined by {N×

[(R_H+R_L)/(R_HR_L)]}, where N is the number of metal patterns, R_H is the resistance of the second test pattern, and R_L is equal to [2R_VIA+R_MP], where R_VIA is the resistance of the metal vias, and R_MP is the resistance of a respective one of the metal patterns.

11. The test method claim 5, wherein an open resistance R_OP indicates the presence of one or more open connections, R_OP being defined by {(N−

X)×

[(R_H+R_L)/(R_HR_L)]+XR_H}, where N is the number of metal patterns, X is the number of open metal patterns, R_H is the resistance of the second test pattern, and R_L is equal to [2R_VIA+R_MP], where R_VIA is the resistance of the metal vias, and R_MP is the resistance of a respective one of the metal patterns.

12. The test method of claim 5, wherein a short resistance R_SH indicates the presence of one or more shorted connections, R_SH being defined by {(N−

X)×

[(R_H+R_L)/(R_HR_L)]+R_MP}, where N is the number of metal patterns, X is the number of shorted metal patterns, R_H is the resistance of the second test pattern, and R_L is equal to [2R_VIA+R_MP], where R_VIA is the resistance of the metal vias, and R_MP is the resistance of a respective one of the metal patterns.

13. The test method of claim 5, wherein the metal patterns forming the first test pattern are made of one selected from the group consisting of aluminum copper, or an alloy of these materials.

14. The test method claim 5, wherein the metal vias are formed from at least one of tungsten and copper.