Transistor sidewall spacer stress modulation

• US 7,132,704 B2
• Filed: 01/13/2005
• Issued: 11/07/2006
• Est. Priority Date: 04/30/2003
• Status: Expired due to Fees

• Current Assignee: North Star Innovations Inc. (Wi-LAN Inc.)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Grudowski, Paul A.
• Primary Examiner(s): Parker, Kenneth
• Assistant Examiner(s): Diaz, Jose R.
• Application Number:
  US11/036,859
• Publication Number:
  US 20050156237A1
• Time in Patent Office: 663 Days
• Field of Search: 257/288, 257/900, 257/E21.626, 257/21.64
• US Class Current: 257/288
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/823468 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/66659 with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/7842 means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate variation of the composition of the channel H01L29/1054
• CPC Class Codes: Y10S 257/90 MOSFET type gate sidewall insulating spacer

Abstract

A semiconductor fabrication process and the resulting integrated circuit include forming a gate electrode (116) over a gate dielectric (104) over a semiconductor substrate (102). A spacer film (124) exhibiting a tensile stress characteristic is deposited over the gate electrode (116). The stress characteristics of at least a portion of the spacer film is then modulated (132, 192) and the spacer film (124) is etched to form sidewall spacers (160, 162) on the gate electrode sidewalls. The spacer film (124) is an LPCVD silicon nitride in one embodiment. Modulating (132) the spacer film (124) includes implanting Xenon or Germanium into the spacers (160) at an implant energy sufficient to break at least some of the silicon nitride bonds. The modulation implant (132) may be performed selectively or non-selectively either before or after etching the spacer film (124).

Claims

1. An integrated circuit, comprising;

first and second transistors, each including a gate electrode over a gate dielectric over a semiconductor substrate;

first spacer structures adjacent sidewalls of the first gate electrode and second spacer structures adjacent sidewalls of the second gate electrode; and

first source/drain regions within the substrate and self-aligned to the first spacer structures and second source/drain regions within the substrate and self-aligned to the second spacer structures, wherein the first and second sidewall spacer structures comprise silicon nitride having a Si/N ratio of less than 0.8 and further wherein the first sidewall spacer structures include a distribution of an impurity selected from Xenon and Germanium.

2. The integrated circuit of claim 1, wherein the second sidewall spacer structures exhibit a tensile stress characteristic that is greater than a corresponding characteristic of the first spacer structure.

3. The integrated circuit of claim 2, wherein the first transistor is a p-channel transistor arid the second transistor is an n-channel transistor.

4. The integrated circuit of claim 1, wherein the first transistor is a p-channel transistor and the second transistor is an n-channel transistor and wherein the second sidewall spacer structures further include a distribution of an impurity selected from Xenon and Germanium.

5. An integrated circuit, comprising:

a plurality of gate electrodes overlying a gate dielectric overlying a semiconductor substrate; and

sidewall spacers laterally disposed on either side of the gate electrodes, wherein at least a portion of the sidewall spacers include sidewall spacers exhibiting a first tensile stress and wherein at least a second portion of the sidewall spacers include sidewall spacers exhibiting a second tensile stress;

wherein the sidewall spacers comprise silicon nitride; and

wherein the second portion of the sidewall spacers further includes an implanted species.

6. The integrated circuit of claim 5, wherein the implanted species comprises Xenon.

7. The integrated circuit of claim 6, wherein the second portion of the sidewall spaces comprises a portion of the integrated circuit overlying PMOS transistors.

8. The integrated circuit of claim 7, wherein the implanted species further comprises Xenon implanted at an energy of at least 180 keV.

9. The integrated circuit of claim 7, wherein the implanted species further comprises Xenon implanted at an implant angle of approximately 45°

10. The integrated circuit of claim 5, wherein the implanted species comprises Germanium.

11. The integrated circuit of claim 10, wherein the implanted species further comprises Germanium implanted at an energy of at least 80 keV and an implant angle of approximately 10°

.

12. A integrated circuit, comprising:

silicon nitride spacers on sidewalls of a gate electrode overlying a semiconductor substrate;

wherein at least some of the sidewall spacers include an implanted species; and

wherein the stress characteristics of the sidewall spacers having the implanted species differ from the stress characteristics of other sidewall spacers.

13. The integrated circuit of claim 12, wherein the silicon nitride spacers comprise silicon nitride formed using a thermal CVD process in which the deposition temperature is in the range of approximately 550 to 750°

C.

14. The integrated circuit of claim 13, wherein the implanted species is selected from Xenon and Germanium.

15. The integrated circuit of claim 14 wherein the Xenon is implanted into the at least some of the sidewall spacers using an implant angle of 10°

or greater.

16. The integrated circuit of claim 15, wherein the Xenon is implanted into at least some of the sidewall spacers using an implant energy not less than 80 keV.

17. The integrated circuit of claim 16, wherein the spaces having the implanted species comprise spacers of n-channel transistors.

18. The integrated circuit of claim 12, wherein the implanted species comprises Germanium implanted at energy of 80 keV and an implant angle of approximately 10°

.