PLL with built-in filter-capacitor leakage-tester with current pump and comparator

• US 7,132,835 B1
• Filed: 02/07/2003
• Issued: 11/07/2006
• Est. Priority Date: 02/07/2003
• Status: Expired due to Fees

• Current Assignee: Diodes Incorporated
• Original Assignee: Pericom Semiconductor Corporation (Diodes Incorporated)
• Inventors: Arcus, Christopher G.
• Primary Examiner(s): DEB, ANJAN K
• Application Number:
  US10/248,683
• Time in Patent Office: 1,369 Days
• Field of Search: 324/523, 324/659, 324/678, 324/76.53
• US Class Current: 324/523
• CPC Class Codes: G01R 31/3004 Current or voltage test
• CPC Class Codes: G01R 31/31727 Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks G01R31/31725 takes precedence; concerning scan test G01R31/318552, for tester hardware G01R31/31922
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/023 in clock generator or timing circuitry
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: H03L 7/093 using special filtering or amplification characteristics in the loop H03L7/087 - H03L7/091 take precedence

Abstract

A filter capacitor within a phase-locked loop (PLL) can be tested using a built-in test circuit. The PLL'"'"'s charge pump is deactivated while a test-current source is activated to supply a test current to the PLL filter capacitor. When the test current is larger than any leakage currents through the capacitor, the capacitor'"'"'s voltage rises above a reference voltage. A test comparator compares the capacitor'"'"'s voltage to the reference voltage and signals a good test result when the capacitor'"'"'s voltage rises above the reference voltage. When leakage current is larger than the test current, the capacitor'"'"'s voltage cannot rise above the reference voltage and the test comparator signal a leakage failure. The test current source can share a bias voltage with the charge pump and can drive the capacitor to a voltage higher than the charge pump does to increase leakage and stress during testing.

Claims

1. A testable phase-locked loop (PLL) comprising:

a reference-clock input for receiving a reference clock from an external clock source;

a feedback clock;

a phase detector that receives the reference clock and the feedback clock;

a filter capacitor on a filter node;

a charge pump, responsive to a phase difference detected by the phase detector, for charging and discharging the filter capacitor on the filter node;

wherein the charge pump comprises;

a first source transistor having a gate receiving a mode signal that indicates when the PLL is operating;

a first bias transistor having a gate receiving a bias voltage;

wherein the first source transistor and the first bias transistor are in series between a power supply and the filter node;

a second source transistor having a gate receiving a mode signal that indicates when the PLL is operating;

a second bias transistor having a gate receiving a second bias voltage;

wherein the second source transistor and the second bias transistor are in series between a ground and the filter node;

a voltage-controlled oscillator (VCO) having the filter node as an input and outputting a clock having a frequency that depends on a filter voltage of the filter node;

wherein the feedback clock is output by the VCO or is derived from the clock output by the VCO;

a test current generator, activated during a leakage test mode, for driving a test current onto the filter node; and

a test comparator, receiving a reference voltage and coupled to the filter node, for comparing the filter voltage to the reference voltage to determine when the test current is able to charge the filter capacitor and to determine when the test current is unable to charge the filter capacitor beyond the reference voltage;

wherein the test comparator outputs a result signal that indicates a leaky filter capacitor when the filter voltage cannot reach the reference voltage,

whereby the filter capacitor within the testable PLL is tested for leakage by the test current generator and the test comparator.

2. The testable phase-locked loop of claim 1 wherein the test current charges the filter node to a stress voltage above a normal operating voltage that the charge pump charges the filter node to during normal PLL operation;

whereby the filter capacitor is stressed to an elevated voltage during leakage testing.

3. The testable phase-locked loop of claim 1 wherein the reference voltage is a voltage between the power supply voltage and the ground.

4. The testable phase-locked loop of claim 1 wherein the bias voltage is intermediate between a power-supply voltage and the ground;

wherein the test current generator receives the bias voltage and generates the test current as a function of the bias voltage;

wherein the charge pump receives the bias voltage and generates a charging current to the filter capacitor as a function of the bias voltage,

whereby the bias voltage is shared by the charge pump and the test current generator.

5. The testable phase-locked loop of claim 4 wherein the bias voltage is about half of the power-supply voltage.

6. The testable phase-locked loop of claim 4 wherein the bias voltage is adjusted for supply-voltage, temperature, and process variations.

7. The testable phase-locked loop of claim 1 wherein the test current generator comprises:

a test source transistor having a gate receiving a test signal that indicates when the filter capacitor is being tested for leakage;

a test bias transistor having a gate receiving a bias voltage;

wherein the test source transistor and the test bias transistor are in series and connected to the filter node.

8. The testable phase-locked loop of claim 7 wherein the test source transistor and the test bias transistor are p-channel transistors connected in series between the power supply and the filter node.

9. The testable phase-locked loop of claim 8 wherein the charge pump further comprises:

a first diverting transistor, coupled to divert current from a node between the first source transistor and the first bias transistor, having a gate receiving a control signal from the charge pump that indicates when to charge the filter capacitor;

a second diverting transistor, coupled to divert current from a node between the second source transistor and the second bias transistor, having a gate receiving a control signal from the charge pump that indicates when to discharge the filter capacitor.

10. The testable phase-locked loop of claim 9 wherein the first source transistor and the first bias transistor are p-channel transistors;

wherein the second source transistor and the second bias transistor are p-channel transistors.

11. The testable phase-locked loop of claim 10 wherein the first and second diverting transistor are p-channel transistors.

12. A method for testing a capacitor in a phase-locked loop (PLL) comprising:

receiving a reference clock and a feedback clock;

detecting a phase difference between the reference clock and the feedback clock using a phase detector of the PLL;

storing charge on the capacitor and outputting a filter voltage of the capacitor;

charging and discharging the capacitor in response to the phase detector during normal PLL operation;

applying the filter voltage as an input to a voltage-controlled oscillator (VCO) and generating the feedback clock in response to the filter voltage from the capacitor;

activating a test charger during a leakage test mode, and charging the capacitor using the test charger during the leakage test mode;

disabling the test charger during normal PLL operation;

determining when the capacitor was successfully charged by the test charger and determining when the test charger was unable to successfully charge the capacitor during the leakage test mode; and

outputting to an external tester a pass/fail signal that indicates a failure when the test charger was unable to successfully charge the capacitor during the leakage test mode,

whereby leakage of the capacitor is tested and the external tester is signaled when the test charger is unable to successfully charge the capacitor.

13. The method for testing a capacitor in a phase-locked loop (PLL) of claim 12 further comprising:

comparing the filter voltage to a reference voltage during the leakage test mode;

charging the capacitor to a filter voltage above the reference voltage during the leakage test mode when no leakage occurs on the capacitor means, but charging the capacitor to a filter voltage below the reference voltage when leakage occurs from the capacitor.