Method and apparatus for avoiding gated diode breakdown in transistor circuits

• US 7,132,873 B2
• Filed: 01/08/2003
• Issued: 11/07/2006
• Est. Priority Date: 01/08/2003
• Status: Active Grant

• Current Assignee: Emosyn America, Inc.
• Original Assignee: Emosyn America, Inc.
• Inventors: Hollmer, Shane C.
• Primary Examiner(s): Wells, Kenneth B.
• Application Number:
  US10/338,551
• Publication Number:
  US 20040130376A1
• Time in Patent Office: 1,399 Days
• Field of Search: 327108-112, 327/309, 327/312, 327/313, 327/316, 327/318, 327319-323, 327/332
• US Class Current: 327/312
• CPC Class Codes: H01L 27/0266 using field effect transistors as protective elements

Abstract

An N-channel transistor protection circuit and method are disclosed that prevent gated diode breakdown in N-channel transistors that have a high voltage on their drain. The disclosed N-channel protection circuit may be switched in a high voltage mode between a high voltage level and a lower rail voltage. A high voltage conversion circuit prevents gated diode breakdown in N-channel transistors by dividing the high voltage across two N-channel transistors, MXU0 and MXU1, such that no transistor exceeds the breakdown voltage, V_breakdown. An intermediate voltage drives the top N-channel transistor, MXU0. The top N-channel transistor, MXU0, is gated with a voltage level that is at least one N-channel threshold, V_tn, below the high voltage level, V_ep, using the intermediate voltage level, nprot. The drain voltage of MXU0 will be at least one N-channel threshold, V_tn, lower than the input voltage level, nprot, and the drain voltage V_d of the bottom N-channel transistor, MXU1, is limited to less than the breakdown voltage, V_breakdown.

Claims

1. A method for avoiding gated diode breakdown in a voltage conversion circuit having at least two N-channel output driver transistors in series, said voltage conversion circuit capable of switching between a high voltage level and a lower rail voltage in a high voltage mode, said method comprising the steps of:

providing a logic input value to select between said high voltage level and said lower rail voltage;

gating one of said at least two N-channel output driver transistors in said high voltage mode with an intermediate voltage level that is between one transistor threshold above said lower rail voltage and one transistor threshold above a breakdown voltage of said at least two N-channel output driver transistors, wherein said intermediate voltage level is generated in said high voltage mode by dropping said high voltage level across at least one N-channel transistor; and

preventing a snapback condition when generating said intermediate voltage level.

2. The method of claim 1, wherein said intermediate voltage level is at least one transistor threshold level below said high voltage level in said high voltage mode.

3. The method of claim 1, wherein said intermediate voltage level is at least one transistor threshold level above said lower rail voltage in a high voltage mode.

4. The method of claim 1, further comprising the step of applying an input signal to a source of a second one of said at least two N-channel output driver transistors.

5. The method of claim 4, wherein said input signal is normally ground.

6. The method of claim 5, wherein said input signal is switched to said lower rail voltage.

7. The method of claim 1, further comprising the step of discharging said intermediate voltage level following said high voltage mode.

8. The method of claim 1, further comprising the step of employing a plurality of stacked transistors to pull a small current from said intermediate voltage level to ensure that said at least one N-channel transistor remains in an ON condition.

9. The method of claim 8, wherein said small current is generated by a current source.

10. The method of claim 1, wherein said lower rail voltage is equal to a positive voltage level or ground.

11. A voltage conversion circuit capable of switching between a high voltage level and a lower rail voltage in a high voltage mode, comprising:

at least two N-channel output driver transistors in series;

a logic input circuit that selects between said high voltage level and said lower rail voltage;

at least one of said at least two N-channel output driver transistors is gated by an intermediate voltage level between one transistor threshold above said lower rail voltage and one transistor threshold above a breakdown voltage of said at least two N-channel output driver transistors, wherein said intermediate voltage level is generated in said high voltage mode by dropping said high voltage level across at least one N-channel transistor; and

means for preventing a snapback condition when generating said intermediate voltage level.

12. The voltage conversion circuit of claim 11, wherein said intermediate voltage level is at least one transistor threshold level below said high voltage level in said high voltage mode.

13. The voltage conversion circuit of claim 11, wherein said intermediate voltage level is at least one transistor threshold level above said lower rail voltage in a high voltage mode.

14. The voltage conversion circuit of claim 11, wherein an input signal is applied to a source of a second one of said at least two N-channel output driver transistors.

15. The voltage conversion circuit of claim 14, wherein said input signal is ground.

16. The voltage conversion circuit of claim 15, wherein said input signal is switched to said lower rail voltage.

17. The voltage conversion circuit of claim 11, wherein said lower rail voltage is equal to a positive voltage level or ground.

18. The voltage conversion circuit of claim 11, further comprising a plurality of stacked transistors to pull a small current from said intermediate voltage level to ensure that said at least one N-channel transistor remains in an ON condition.