Large gain range, high linearity, low noise MOS VGA

• US 7,132,888 B2
• Filed: 03/26/2004
• Issued: 11/07/2006
• Est. Priority Date: 11/12/1998
• Status: Expired due to Term

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Behzad, Arya R.
• Primary Examiner(s): NGUYEN, KHANH V
• Application Number:
  US10/809,838
• Publication Number:
  US 20040212417A1
• Time in Patent Office: 956 Days
• Field of Search: 330/254
• US Class Current: 330/254
• CPC Class Codes: H01F 17/0006 Printed inductances printed coils for dynamo-electric machines H02K3/26; printed circuits H05K
• CPC Class Codes: H01F 17/0013 with stacked layers
• CPC Class Codes: H01F 2017/0026 Multilayer LC-filter
• CPC Class Codes: H01F 2017/0053 with means to reduce eddy currents
• CPC Class Codes: H01F 2021/125 Printed variable inductor with taps, e.g. for VCO
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 27/0248 for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
• CPC Class Codes: H01L 27/08 including only semiconductor components of a single kind
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H03B 2201/025 the means being an electronic switch for switching in or out oscillator elements
• CPC Class Codes: H03B 2201/0266 the means comprising a transistor
• CPC Class Codes: H03B 5/364 the amplifier comprising field effect transistors H03B5/366 takes precedence
• CPC Class Codes: H03D 7/161 all the frequency changers being connected in cascade
• CPC Class Codes: H03D 7/18 Modifications of frequency-changers for eliminating image frequencies H03D7/16 takes precedence
• CPC Class Codes: H03F 1/3211 in differential amplifiers
• CPC Class Codes: H03G 1/0029 using FETs
• CPC Class Codes: H03H 11/1291 Current or voltage controlled filters
• CPC Class Codes: H03J 1/0075 where the receiving frequencies of the stations are stored in a permanent memory, e.g. ROM
• CPC Class Codes: H03J 2200/10 : Tuning of a resonator by means of digitally controlled capacitor bank
• CPC Class Codes: H03J 3/04 : Arrangements for compensating for variations of physical values, e.g. temperature
• CPC Class Codes: H03J 3/08 : by varying a second parameter simultaneously with the tuning, e.g. coupling bandpass filter
• CPC Class Codes: H03J 3/185 : with varactors, i.e. voltage variable reactive diodes
• CPC Class Codes: H03L 1/023 : by using voltage variable capacitance diodes
• CPC Class Codes: H03L 7/10 : for assuring initial synchronisation or for broadening the capture range
• CPC Class Codes: H03L 7/104 : using an additional signal from outside the loop for setting or controlling a parameter in the loop H03L7/107, H03L7/12 take precedence
• CPC Class Codes: H03L 7/23 : with pulse counters or frequency dividers

Abstract

An integrated receiver with channel selection and image rejection is substantially implemented on a single CMOS integrated circuit. A receiver front end provides programable attenuation and a programable gain low noise amplifier. LC filters integrated onto the substrate in conjunction with image reject mixers provide image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. Active filters utilize multi track spiral inductors with shields to increase circuit Q. Frequency planning provides additional image rejection. Local oscillator signal generation methods on chip reduce distortion. A PLL generates needed out of band LO signals. Direct synthesis generates in band LO signals. PLL VCOs are centered automatically. A differential crystal oscillator provides a frequency reference. Differential signal transmission throughout the receiver is used. ESD protection is provided by a pad ring and ESD clamping structure. Shunts utilize a gate boosting at each pin to discharge ESD build up. An IF VGA utilizes distortion cancellation achieved with cross coupled differential pair amplifiers having their V_ds dynamically modified in conjunction with current steering of the differential pairs sources.

Claims

1. A gain circuit, comprising:

a substrate;

a first differential pair amplifier disposed upon the substrate and coupled to a first circuit output having a gain contributing to circuit gain in direct proportion to the first differential pair amplifier gain;

a second differential pair amplifier disposed upon the substrate and coupled to a second circuit output having a gain, and coupled to the first differential amplifier such that an increase in second differential pair amplifier gain contributes to a decrease in the circuit gain; and

a variable voltage source coupled to the circuit outputs, a voltage output of the variable voltage source determining respective drain source voltages on the first differential pair and the second differential pair based on a differential input signal received at the first differential pair amplifier and the second differential pair amplifier, and thereby controlling the gain of the first differential pair and the gain of the second differential pair,

wherein the variable voltage source controls a transconductance of the gain circuit so as to improve linearity of the gain circuit.

2. The gain circuit of claim 1, wherein the first differential pair amplifier includes:

a first transistor; and

a second transistor,

wherein the variable voltage source controls a transconductance of the first transistor so as to flatten a transconductance transfer characteristic of the first transistor; and

wherein the variable voltage source controls a transconductance of the second transistor so as to flatten a transconductance transfer characteristic of the second transistor.

3. The gain circuit of claim 1, wherein the second differential pair amplifier includes:

a first transistor; and

a second transistor,

wherein the variable voltage source controls a transconductance of the first transistor so as to flatten a transconductance transfer characteristic of the first transistor; and

wherein the variable voltage source controls a transconductance of the second transistor so as to flatten a transconductance transfer characteristic of the second transistor.

4. The gain circuit of claim 1, wherein:

the first differential pair amplifier includes

a first transistor; and

a second transistor,

wherein the variable voltage source controls a transconductance of the first transistor so as to flatten a transconductance transfer characteristic of the first transistor; and

wherein the variable voltage source controls a transconductance of the second transistor so as to flatten a transconductance transfer characteristic of the second transistor; and

the second differential pair amplifier includes

a third transistor; and

a fourth transistor,

wherein the variable voltage source controls a transconductance of the third transistor so as to flatten a transconductance transfer characteristic of the third transistor; and

wherein the variable voltage source controls a transconductance of the fourth transistor so as to flatten a transconductance transfer characteristic of the fourth transistor.

5. The gain circuit of claim 4, wherein drain source voltages of the first, second, third, and fourth transistors are adjusted so as to flatten corresponding transfer characteristics of the first, second, third, and fourth transistors.

6. The gain circuit of claim 5, wherein the drain source voltages across the first, second, third, and fourth transistors are reduced upon reducing a DC voltage at the output of the first and second differential pairs.

7. The gain circuit of claim 5, wherein the transconductance transfer characteristic of each of the first, second, third, and fourth transistors is a relationship between the transconductance of the transistor versus a gate source voltage of the transistor as the drain source voltage across the transistor is varied.

8. A method for providing, over a wide range of input signal voltages, variable gain amplification having a linear change in output current gain at a differential current output port as a function of a change in differential voltage input at a differential voltage input port, the variable gain amplification provided by a variable gain amplifier responsive to the differential voltage input, the method comprising the steps of:

receiving an input signal voltage; and

adjusting a transconductance of the variable gain amplifier in response to the input signal voltage so as to flatten a transconductance transfer characteristic of the variable gain amplifier, the adjusting step including reducing a drain source voltage across the variable gain amplifier for increasing amplitude of the input signal voltage.

9. The method of claim 8, wherein the adjusting step includes the steps of:

adjusting a transconductance of a first common source differential pair amplifier of the variable gain amplifier so as to flatten a transconductance transfer characteristic of the first common source differential pair amplifier; and

adjusting a transconductance of a second common source differential pair amplifier of the variable gain amplifier so as to flatten a transconductance transfer characteristic of the second common source differential pair amplifier.

10. The method of claim 9, wherein the adjusting a transconductance of the first common source differential pair amplifier includes the steps of:

adjusting a transconductance of a first transistor so as to flatten, a transconductance characteristic of the first transistor; and

adjusting a transconductance of a second transistor so as to flatten a transconductance characteristic of the second transistor,

wherein the first and second transistor share a common source and are connected to form the first common source differential pair amplifier.