Apparatus and method for data transmission

• US 7,133,014 B2
• Filed: 05/07/2002
• Issued: 11/07/2006
• Est. Priority Date: 01/14/2002
• Status: Expired due to Term

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Philips LCD Company Limited (LG Display Co., Ltd.)
• Inventors: Lee, Seok Woo, Song, Jin Kyoung
• Primary Examiner(s): CHANG, KENT WU
• Application Number:
  US10/139,354
• Publication Number:
  US 20030132926A1
• Time in Patent Office: 1,645 Days
• Field of Search: 345211-215, 345 98-100, 345204-208, 345/87
• US Class Current: 345/98
• CPC Class Codes: G09G 2310/0289 Details of voltage level shifters arranged for use in a driving circuit
• CPC Class Codes: G09G 2310/08 Details of timing specific for flat panels, other than clock recovery
• CPC Class Codes: G09G 2330/06 Handling electromagnetic interferences [EMI], covering emitted as well as received electromagnetic radiation
• CPC Class Codes: G09G 3/20 for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
• CPC Class Codes: G09G 3/3611 Control of matrices with row and column drivers
• CPC Class Codes: H04B 15/04 the interference being caused by substantially sinusoidal oscillations, e.g. in a receiver or in a tape-recorder

Abstract

The present invention discloses a data transmission apparatus and method to lower a data transmission voltage for eliminating EMI. In the data driving apparatus, a timing controller aligns input pixel data, lowers input data voltages of the input pixel data, and outputs to a plurality of data transmission lines. A data driver raises the lowered input data voltages for driving the liquid crystal display panel and then converts into analog pixel voltage signals to supply the analog pixel voltage signals to the data lines.

Claims

1. A data transmission apparatus, comprising:

a data interface receiving n-bit parallel input data having an input data voltage, lowering the n-bit parallel input data to a transmission voltage, and outputting the n-bit parallel input data having the transmission voltage to a plurality of data transmission lines, n being a positive integer and the n-bit parallel input data being lowered to the transmission voltage by a first circuit, the first circuit including a first resistor connected in series with each of the data transmission lines; and

a data receiver receiving the n-bit parallel input data having the transmission voltage from the data transmission lines, and raising the n-bit parallel input data to the input data voltage for driving a liquid crystal display panel, the n-bit parallel input data being raised to the input data voltage by a second circuit, the second circuit including a voltage amplifier connected to each of the data transmission lines.

2. The data transmission apparatus according to claim 1, wherein the first circuit further includes:

a second resistor arranged in parallel at each of the data transmission lines and having a resistance value lower than the first resistor.

3. The data transmission apparatus according to claim 2, wherein the first resistor is arranged at an output terminal of the data interface, and the second resistor is arranged at an input terminal of the data receiver.

4. The data transmission apparatus according to claim 2, wherein the first and second resistors are arranged at an output terminal of the data interface.

17. The data transmission apparatus according to claim 1, wherein the input data voltage is at least 10 times as large as the transmission voltage.

5. A data transmission method comprising:

lowering an input data voltage of an n-bit parallel input data and outputting the n-bit parallel input data having the lowered input data voltage to a plurality of data transmission lines; and

raising the lowered input voltage of the n-bit parallel input data back to the input data voltage for driving a liquid crystal display panel,

wherein the n-bit parallel input data voltage is lowered by a first resistor connected in series with each of the data transmission lines.

6. A data driving apparatus of a liquid crystal display for driving a plurality of data lines of a liquid crystal display panel, the apparatus comprising:

a timing controller for aligning n-bit parallel input pixel data having an input data voltage, for lowering the n-bit parallel input pixel data to a transmission voltage, and for outputting the n-bit parallel input pixel data having the transmission voltage to a plurality of data transmission lines, the timing controller including a first circuit for lowering the n-bit parallel input pixel data to the transmission voltage, the first circuit having a first resistor connected in series with each of the data transmission lines; and

a data driver for raising the n-bit parallel input pixel data back to the input data voltage for driving the liquid crystal display panel and for converting the n-bit parallel input pixel data having the input data voltage into analog pixel voltage signals to apply the analog pixel voltage signals to the data lines, the data driver including a second circuit for the raising the n-bit parallel input pixel data to the input data voltage, the second circuit including a voltage amplifier connected to each of the data transmission lines.

7. The data driving apparatus according to claim 6, wherein the first circuit further includes:

a second resistor arranged in parallel with each of the data transmission lines and having a resistance value lower than the first resistor.

8. The data driving apparatus according to claim 7, wherein the first resistor is arranged at an output terminal of the timing controller, and the second resistor is arranged at an input terminal of the data driver.

9. The data driving apparatus according to claim 7, wherein the first and second resistors are arranged at an output terminal of the timing controller.

10. The data driving apparatus according to claim 6, wherein the timing controller generates a plurality of control signals for controlling driving of the data driver and lowers voltages of the control signals by using a third circuit to output to a plurality of control signal transmission lines.

11. The data driving apparatus according to claim 10, wherein the third circuit includes:

a third resistor arranged in series at each of the control signal transmission lines; and

a fourth resistor arranged in parallel at each of the control signal transmission lines and having a resistance value lower than the third resistor.

12. The data driving apparatus according to claim 11, wherein the third resistor is arranged at an output terminal of the timing controller, and the fourth resistor is arranged at an input terminal of the data driver.

13. The data driving apparatus according to claim 12, wherein the third resistor is incorporated into the timing controller, and the fourth resistor is incorporated into the data driver.

14. The data driving apparatus according to claim 11, wherein the third and fourth resistors are arranged at an output terminal of the timing controller.

15. The data driving apparatus according to claim 14, wherein both the third and fourth resistors are incorporated into the timing controller.

16. The data driving apparatus according to claim 6, wherein the data driver includes:

a data-driving unit for converting the pixel data having the input data voltage into analog pixel voltage signals to supply the analog pixel voltage signals to the data lines.

18. The data driving apparatus according to claim 6, wherein the input data voltage is at least 10 times as large as the transmission voltage.

19. The data driving apparatus according to claim 6, wherein the timing controller generates a plurality of control signals for controlling driving of the data driver and outputs the control signals to a plurality of control signal transmission lines.