Image sensor circuits including sampling circuits used therein for performing correlated double sampling

• US 7,133,074 B1
• Filed: 09/28/1999
• Issued: 11/07/2006
• Est. Priority Date: 09/28/1999
• Status: Expired due to Term

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Zoran Corporation (Qualcomm, Inc.)
• Inventors: Harris, Brannon, Brehmer, Kevin E.
• Primary Examiner(s): Srivastava, Vivek
• Assistant Examiner(s): MISLEH, JUSTIN P
• Application Number:
  US09/406,979
• Time in Patent Office: 2,597 Days
• Field of Search: 348/300, 348/301, 348/302, 348/303, 348/304, 348/305, 348/306, 348/307, 348/308, 348/294, 348/241, 348/243, 257/291, 257/292, 250/208.1, 327/91, 327/94, 327/95
• US Class Current: 348/308
• CPC Class Codes: H04N 25/00 Circuitry of solid-state image sensors [SSIS]; Control thereof

Abstract

A CMOS image sensor circuit includes an array of sensing elements which integrate electrical charge according to the light intensity thereon. In order to measure the accumulated charge voltage at the individual sensing elements, and thus obtain the image data from the array, a sampling circuit is provided. The sampling circuit operates using a high-gain amplification stage and an auto-zero amplifier to perform correlated double sampling, which enables non-linear influences which may arise in the array to be reduced in the measuring process. The sampling circuit can also include a sample and hold circuit arranged to account for a feed-through effect arising from pre-charge circuitry in the sensing elements. The sample and hold circuit can be included within the feed-back loop of the high-gain amplification stage for further increases in linear performance.

Claims

1. A sampling circuit for an image sensing circuit having a photosensitive element which develops a photo sensing node voltage according to incident light, the sampling circuit comprising:

an amplifier circuit having an output and having a differential input transistor pair circuit with said photo sensing node voltage as a first input and with a feedback signal as a second input; and

a sample and hold circuit having an input coupled to the output of the amplifier circuit, and having an output; and

a clamping circuit coupled to the output of the sample and hold circuit and having an output carrying a signal representing a double correlated sample voltage difference at said photo sensing node;

wherein the feedback signal is received by the second input of the amplifier circuit from the output of the sample and hold.

2. A sampling circuit as claimed in claim 1, wherein a source follower circuit coupled within said feedback loop is used to couple the output of the sample and hold circuit to said clamping circuit.

3. A sampling circuit as claimed in claim 2, wherein said clamping circuit comprises an auto-zero amplifier circuit having a feedback loop which includes a first capacitive storage element coupled in parallel with a switching element controlled by a clamp signal.

4. A sampling circuit as claimed in claim 2, wherein the feedback loop is arranged so that the amplifier circuit has a gain of greater than unity.

5. A sampling circuit as claimed in claim 1, wherein a plurality of image sensing circuits are arranged in an array, each forming a pixel circuit of an image sensor, and wherein each pixel circuit includes a said photo sensitive element, a reset switching element and a said differential input transistor pair as part of said amplifier circuit, and wherein the sample and hold circuit and the clamping circuit are shared by a plurality of pixel circuits in the image sensor array.

6. A sampling circuit as claimed in claim 1, wherein the image sensing circuit, amplifier circuit, sample and hold circuit and clamping circuit are constructed in the same integrated circuit using CMOS fabrication technology.

7. A sampling circuit for an image sensing circuit having a photosensitive element which develops a photo sensing node voltage according to incident light, the sampling circuit comprising:

an amplifier circuit having a differential input transistor pair circuit with said photo sensing node voltage as one input;

a sample and hold circuit coupled to an output of the amplifier circuit; and

a clamping circuit coupled to an output of the sample and hold circuit and produce an output signal representing a double correlated sample voltage difference at said photo sensing node;

wherein the amplifier circuit is coupled to the output of the sample and hold circuit as a second input, to form a feedback loop;

wherein a source follower circuit coupled within said feedback loop is used to couple the output of the sample and hold circuit to said clamping circuit;

wherein said clamping circuit comprises an auto-zero amplifier circuit having a feedback loop which includes a first capacitive storage element coupled in parallel with a switching element controlled by a clamp signal; and

wherein the amplifier circuit of the clamping circuit has a first input coupled to a reference voltage and a second input coupled by way of a second capacitive element to said sample and hold circuit output, and wherein said clamping circuit is controlled by said clamp signal such that in a first state the output of the clamping circuit amplifier is fixed by said reference voltage and in a second state the clamping circuit output changes in accordance with said sample and hold circuit output from a baseline of the fixed reference voltage output.

8. An image sensor circuit having a two dimensional array of light sensitive pixel circuits, each pixel circuit comprising a photosensitive element and a reset switching element coupled to a light sensing node, a differential input transistor pair having a first input thereof coupled to said light sensing node, and an enable switching element coupled to selectively block output from the differential input transistor pair, the image sensing circuit further comprising sampling circuitry for producing output signals corresponding to light incident on each of the respective pixel circuits,

wherein said sampling circuitry provides a feedback path defined from the output of the differential input transistor pair to a second input of said differential input transistor pair of each of said pixel circuits, and

wherein said sampling circuitry includes a sample and hold circuit within the feedback path having an input coupled to receive a signal from the output from the differential input transistor pair and sample the received signal, and having an output coupled to transfer the sampled signal to the second input of said differential input transistor pair.

9. An image sensor circuit as claimed in claim 8, wherein said sampling circuitry further includes a source follower circuit coupled within said feedback path which provides an input to a clamping circuit.

10. An image sensor circuit as claimed in claim 9, wherein said clamping circuit comprises an auto-zero amplifier circuit.

11. An image sensor circuit as claimed in claim 8, wherein the image sensor array is implemented with CMOS technology.

12. An image sensor array as claimed in claim 8, wherein the photosensitive element comprises a photo-diode.

13. An image sensor array as claimed in claim 8, wherein the photosensitive element comprises a photo-gate transistor.

14. An image sensor circuit having a two dimensional array of light sensitive pixel circuits, each pixel circuit comprising a photosensitive element and a reset switching element coupled to a light sensing node, a differential input transistor pair having a first input thereof coupled to said light sensing node, and an enable switching element coupled to selectively block output from the differential input transistor pair, the image sensing circuit further comprising sampling circuitry for producing output signals corresponding to light incident on each of the respective pixel circuits;

wherein said sampling circuitry provides a feedback path to a second input of said differential input transistor pair of each of said pixel circuits;

wherein said sampling circuitry includes a sample and hold circuit coupled within said feedback path;

wherein said sampling circuitry further includes a source follower circuit coupled within said feedback path which provides an input to a clamping circuit; and

wherein said clamping circuit comprises an auto-zero amplifier circuit having a feedback loop which includes a first capacitive storage element coupled in parallel with a switching element controlled by a clamp signal, and wherein the auto-zero amplifier circuit of the clamping circuit has a first input coupled to a reference voltage and a second input coupled by way of a second capacitive element to an output of said sample and hold circuit, and wherein said clamping circuit is controllable by said clamp signal such that in a first state the output of the clamping circuit auto-zero amplifier is fixed by said reference voltage and in a second state the clamping circuit output changes in accordance with the input received from said sample and hold circuit from a baseline of said fixed reference voltage output.

15. In an image sensor circuit having an array of pixels including light sensing nodes at each of which a change in voltage can be imparted by exposure to a light source, a method for obtaining output signals representing the voltage changes at the light sensing nodes in order to obtain image data, comprising:

at each said pixel providing a differential amplifier circuit with an input driven by the voltage on the respective light sensing node to produce an amplifier output;

providing a sample and hold circuit with an input coupled to selectively receive the amplifier output of a said pixel amplifier circuit in the array, the sample and hold circuit being controlled by a first control signal input and producing an output signal;

coupling the sample and hold circuit output to a second input of the differential amplifier within a feedback loop;

providing a clamping circuit coupled to the sample and hold circuit output, the clamping circuit producing an output according to the received sample and hold signal output and a second control signal; and

controlling the first and second control signals to the sample and hold circuit and the clamping circuit respectively so as to perform correlated double sampling of the voltage at the respective light sensing node so as to obtain a representation of the change of voltage thereat imparted substantially only by exposure to light.

16. A sampling circuit for an image sensing circuit having a photosensitive element which develops a photo sensing node voltage according to incident light, the sampling circuit comprising:

a feedback loop amplifier circuit having said photo sensing node voltage as one input and producing an output, and a sample and hold circuit having an input coupled to receive the amplifier circuit output and the sample and hold circuit having an output coupled to transfer a sampled value to a second input of the feedback loop amplifier circuit, to form a feedback path containing the sample and hold circuit in feedback path;

a clamping circuit coupled to the output from the sample and hold circuit and which produces an output signal representing a double correlated sample voltage difference at said photo sensing node.

17. A sampling circuit as claimed in claim 16, wherein the amplifier circuit includes a source follower circuit coupled within the feedback loop thereof, the source follower circuit supplying output to the clamping circuit.

18. A sampling circuit as claimed in claim 17, wherein the feedback of said feedback loop amplifier is arranged so that the amplifier circuit has a gain of greater than unity.

19. A sampling circuit as claimed in claim 16, wherein said clamping circuit comprises an auto-zero amplifier circuit.

20. A sampling circuit as claimed in claim 19, wherein the auto-zero amplifier circuit has a feedback loop which includes a first capacitive storage element coupled in parallel with a switching element controlled by a clamp signal.

21. A sampling circuit for an image sensing circuit having a photosensitive element which develops a photo sensing node voltage according to incident light, the sampling circuit comprising:

a feedback loop amplifier circuit having said photo sensing node voltage as an input; and

a clamping circuit coupled to an output from the feedback loop amplifier circuit and produce an output signal representing a double correlated sample voltage difference at said photo sensing node;

wherein said clamping circuit comprises an auto-zero amplifier circuit;

wherein the auto-zero amplifier circuit has a feedback loop which includes a first capacitive storage element coupled in parallel with a switching element controlled by a clamp signal; and

wherein the amplifier circuit of the clamping circuit has a first input coupled to a reference voltage and a second input coupled by way of a second capacitive element to said output from the feedback loop amplifier, and wherein said clamping circuit is controlled by a clamp signal such that in a first state the output of the clamping circuit amplifier is fixed by said reference voltage and in a second state the clamping circuit output changes in accordance with said feedback loop amplifier output from a baseline of the fixed reference voltage output.