Integrated circuit packages with sandwiched capacitors

• US 7,133,294 B2
• Filed: 03/15/2005
• Issued: 11/07/2006
• Est. Priority Date: 12/03/2001
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Pinello, William P., Xie, Hong, Sankman, Robert L., Figueroa, David G., Patel, Priyavadan R., Chung, Chee-Yee, Li, Yuan-Liang
• Primary Examiner(s): Vigushin, John B.
• Application Number:
  US11/080,126
• Publication Number:
  US 20050156280A1
• Time in Patent Office: 602 Days
• Field of Search: None
• US Class Current: 361/782
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16265 the item being a discrete passive component
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 24/81 using a bump connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01047 Silver [Ag]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/01082 Lead [Pb]
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/19041 being a capacitor
• CPC Class Codes: H01L 2924/19103 interposed between the semiconductor or solid-state device and the die mounting substrate, i.e. chip-on-passive
• CPC Class Codes: H01L 2924/19104 : on the semiconductor or solid-state device, i.e. passive-on-chip
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/30107 : Inductance

Abstract

To provide high-speed, low inductance capacitive decoupling, an integrated circuit (IC) package includes capacitors positioned within the mounting region between a die and an IC package substrate. A variety of types and sizes of capacitors and substrates can be employed in a variety of geometrical arrangements. In some embodiments, capacitors are sandwiched between die terminals or bumps and the substrate conductors or pads, while in other embodiments, capacitors are positioned between bar-type conductors on the surface of the IC package substrate. Methods of fabrication, as well as application of the package to an electronic assembly and to an electronic system, are also described.

Claims

1. An integrated circuit (IC) package comprising:

a substrate having a substantially planar upper surface entirely throughout an IC mounting region and a plurality of conductors within the IC mounting region on the upper surface;

at least one capacitor within the IC mounting region, wherein the at least one capacitor comprises top and bottom surfaces, each having a plurality of terminals of first and second polarity types, wherein a selected terminal of first polarity type on the bottom surface is physically and electrically coupled to a first conductor of the plurality of conductors, wherein a selected terminal of second polarity type on the bottom surface is physically and electrically coupled to a second conductor of the plurality of conductors, and wherein the at least one capacitor is mounted atop and at a diagonal to the first and second conductors to which it is electrically coupled; and

an IC comprising a plurality of IC terminals on a surface thereof, wherein the IC terminals are physically and electrically coupled to selected terminals of first and second polarity types on the top surface of the capacitor.

2. The IC package recited in claim 1, wherein the first conductor is to couple to a first potential, and the second conductor is to couple to a second potential.

3. The IC package recited in claim 1, wherein the at least one capacitor is mounted atop at least three conductors.

4. The IC package recited in claim 1, wherein the at least one capacitor is a capacitor array.

5. The IC package recited in claim 1, wherein the plurality of capacitor terminals are disposed over substantially the entire top and bottom surfaces.

6. The IC package recited in claim 1, wherein the plurality of conductors are substantially parallel to one another.

7. The IC package recited in claim 1 and comprising a plurality of capacitors distributed substantially throughout the IC mounting region, each capacitor being in electrical contact with at least one of the conductors.

8. The IC package recited in claim 1, wherein the conductors include pads.

9. An integrated circuit (IC) package comprising:

a substrate having a substantially planar upper surface entirely throughout an IC mounting region and a plurality of conductors within the IC mounting region on the upper surface;

a plurality of capacitors distributed substantially throughout the IC mounting region, wherein each capacitor comprises top and bottom surfaces, each having a plurality of terminals of first and second polarity types, wherein a selected terminal of first polarity type on the bottom surface of each capacitor is physically and electrically coupled to a first conductor of the plurality of conductors, wherein a selected terminal of second polarity type on the bottom surface of each capacitor is physically and electrically coupled to a second conductor of the plurality of conductors; and

an IC comprising a plurality of IC terminals on a surface thereof, wherein the IC terminals are physically and electrically coupled to selected terminals of first and second polarity types on the top surface of the capacitors.

10. The IC package recited in claim 9, wherein the plurality of capacitors comprises a plurality of sets of capacitors, each set comprising one or more capacitors aligned substantially end-to-end.

11. The IC package recited in claim 9, wherein the first conductor is to couple to a first potential, and the second conductor is to couple to a second potential.

12. The IC package recited in claim 9, wherein at least one capacitor is mounted atop at least three conductors.

13. The IC package recited in claim 9, wherein at least one capacitor is a capacitor array.

14. The IC package recited in claim 9, wherein the plurality of capacitor terminals are disposed over substantially, the entire top and bottom surfaces.

15. The IC package recited in claim 9, wherein the plurality of conductors are substantially parallel to one another.

16. The IC package recited in claim 9, wherein the conductors include pads.

17. An integrated circuit (IC) package comprising:

a substrate having a substantially planar upper surface entirely throughout an IC mounting region and a plurality of conductors within the IC mounting region on the upper surface;

a plurality of capacitors within the IC mounting region, wherein each capacitor comprises top and bottom surfaces, each having terminals of first and second polarity types, wherein a terminal of first polarity type on the bottom surface is physically and electrically coupled to a first conductor of the plurality of conductors, wherein a terminal of second polarity type on the bottom surface is physically and electrically coupled to a second conductor of the plurality of conductors; and

an IC comprising a plurality of IC terminals on a surface thereof, wherein the IC terminals are physically and electrically coupled to terminals of first and second polarity types on the top surface of the capacitors.

18. The IC package recited in claim 17, wherein the first conductor is to couple to a first potential, and the second conductor is to couple to a second potential.

19. The IC package recited in claim 17, wherein the at least one capacitor is mounted atop at least three conductors.

20. The IC package recited in claim 17, wherein the at least one capacitor is a capacitor array.

21. The IC package recited in claim 17, wherein the plurality of capacitor terminals are disposed over substantially the entire top and bottom surfaces.

22. The IC package recited in claim 17, wherein the plurality of conductors are substantially parallel to one another.

23. The IC package recited in claim 17 and comprising a plurality of capacitors distributed substantially throughout the IC mounting region, each capacitor being in electrical contact with at least one of the conductors.

24. The IC package recited in claim 17, wherein the conductors include pads.