Video optical multiplexer

• US 7,133,401 B2
• Filed: 10/01/2001
• Issued: 11/07/2006
• Est. Priority Date: 10/01/2001
• Status: Expired due to Fees

• Current Assignee: General Electric Company
• Original Assignee: General Electric Company
• Inventors: Huntley, Chris
• Primary Examiner(s): Nguyen, Chau
• Assistant Examiner(s): Davis, Cynthia L.
• Application Number:
  US09/968,059
• Publication Number:
  US 20030095210A1
• Time in Patent Office: 1,863 Days
• Field of Search: None
• US Class Current: 370/389
• CPC Class Codes: H04N 5/268 Signal distribution or switching

Abstract

An optical multiplexer is provided that operates in a synchronous optical network (SONET). The multiplexer includes a plurality of inputs and a processor operationally coupled to the inputs. The multiplexer also includes a plurality of optical outputs coupled to the inputs via the processor, wherein the processor is configured to receive data from at least two of the plurality of inputs. The processor is also configured to packetize the received data and route the packetized data to at least two of the plurality of optical outputs.

Claims

1. A video optical multiplexer that operates in a synchronous optical network (SONET) comprising:

a plurality of video inputs;

a processor operationally coupled to said video inputs;

a plurality of optical video outputs coupled to said video inputs via said processor, said processor configured to;

receive video data from at least two of said plurality of optical video inputs;

packetize the received video data; and

route the packetized video data to at least two of said plurality of optical video outputs, said processor routing each packetized video data package based upon a video network address (VNA) contained in each packet using a VNA lookup table; and

a mapper coupled to said processor and configured to track a port that outputs a request to receive a video signal, wherein said mapper configured to determine a spare capacity of a path between said mapper and the port by obtaining a value indicated within the request to receive the video signal.

2. A multiplexer in accordance with claim 1 further comprising a Field Programmable Logic Gate Array (FPGA) operationally coupled to said processor, said FPGA configured to detect a start of field (SOF) data pattern for the packetized video data.

3. A multiplexer in accordance with claim 2 wherein said FPGA comprises a pacer circuit configured to pace an output of the routed packetized video data.

4. A multiplexer in accordance with claim 3 wherein said pacer circuit configured to:

output the routed packetized video data at a first resolution when the packetized video data is interlaced; and

output the routed packetized video data at a second resolution when the packetized video data is non-interlaced.

5. A multiplexer in accordance with claim 3 wherein said pacer circuit configured to:

output the routed packetized video data at a first resolution when the packetized video data is interlaced; and

output the routed packetized video data at a second resolution when the packetized video data is non-interlaced, the second resolution approximately one-half the first resolution.

6. A multiplexer in accordance with claim 1 further comprising:

at least one optical audio input operationally coupled to said processor; and

at least one optical audio output operationally coupled to said processor, said processor further configured to packetize audio data received from said optical audio input in a packet of equal size to a packet size of said packetized video data.

7. A multiplexer in accordance with claim 6 wherein each said audio packet and each said video packet comprise between twenty bytes per packet and thirty bytes per packet.

8. A multiplexer in accordance with claim 7 wherein each said audio packet and each said video packet comprise approximately twenty-five bytes per packet.

9. A multiplexer in accordance with claim 7 wherein each said audio packet and each said video packet comprise twenty-five bytes per packet.

10. A multiplexer in accordance with claim 1 wherein said plurality of optical video inputs and said plurality of optical video outputs are connected in a linear topology.

11. A multiplexer in accordance with claim 1 wherein each said optical video input is configured to:

receive an analog video input from an analog video source; and

output to said processor an optical digital video signal.

12. A multiplexer in accordance with claim 1 wherein each optical video output is configured to:

receive from said processor an optical digital video signal; and

output an analog video signal.

13. A multiplexer in accordance with claim 1 wherein said plurality of optical video inputs and said plurality of optical video outputs are connected in a tree topology.

14. A multiplexer in accordance with claim 1 wherein each VNA comprises thirteen bits.

15. A multiplexer in accordance with claim 1 wherein said mapper configured to determine the spare capacity by comparing the value with a rate at which a port of said mapper remains idle.

16. A method for operating a synchronous optical network (SONET), said method comprising:

providing a plurality of optical video inputs;

operationally coupling a processor to the optical video inputs;

operationally coupling a plurality of optical video outputs to the optical video inputs via the processor;

configuring the processor to;

receive video data from at least two of the plurality of optical video inputs;

packetize the received video data;

route the packetized video data to at least two of the plurality of optical video outputs; and

route, by using a video network address (VNA) lookup table, each packet of the packetized video data based upon a VNA contained in each packet of the packetized video data;

tracking, by a mapper coupled to the processor, a port that outputs a request to receive a video signal; and

determining, by the mapper, a spare capacity of a path between the mapper and the port by obtaining a value indicated within the request to receive the video signal.

17. A method in accordance with claim 16 further comprising:

operationally coupling a Field Programmable Logic Gate Array (FPGA) operationally coupled to the processor; and

configuring the FPGA to detect a start of field (SOF) data pattern for the packetized video data.

18. A method in accordance with claim 17 further comprising:

providing a pacer circuit in the FPGA; and

configuring the pacer circuit to pace an output of the routed packetized video data.

19. A method in accordance with claim 18 further comprising configuring the pacer circuit to:

output the routed packetized video data at a first resolution when the packetized video data is interlaced; and

output the routed packetized video data at a second resolution when the packetized video data is non-interlaced.

20. A method in accordance with claim 18 further comprising configuring the pacer circuit to:

output the routed packetized video data at a first resolution when the packetized video data is interlaced; and

output the routed packetized video data at a second resolution when the packetized video data is non-interlaced, wherein the second resolution is approximately one-half the first resolution.

21. A method in accordance with claim 16 further comprising:

operationally coupling at least one optical audio input to the processor;

operationally coupling at least one optical audio output to the processor; and

configuring the processor to packetized audio data received from the optical audio input in a packet of equal size to a packet size of the packetized video data.

22. A method in accordance with claim 21 wherein each audio packet and each video packet comprise between twenty bytes per packet and thirty bytes per packet.

23. A method in accordance with claim 22 wherein each audio packet and each video packet comprise approximately twenty-five bytes per packet.

24. A method in accordance with claim 23 wherein each audio packet and each video packet comprise twenty-five bytes per packet.

25. A method in accordance with claim 16 further comprising connecting the plurality of optical video inputs and the plurality of optical video outputs in a linear topology.

26. A method in accordance with claim 16 further comprising configuring each optical video input to:

receive an analog video input from an analog video source; and

output to the processor an optical digital video signal.

27. A method in accordance with claim 16 further comprising configuring each optical video output to:

receive from the processor an optical digital video signal; and

output an analog video signal.

28. A method in accordance with claim 16 further comprising connecting the plurality of optical video inputs and the plurality of optical video outputs in a tree topology.

29. A method in accordance with claim 16 wherein each VNA comprises thirteen bits.

30. A method in accordance with claim 16, wherein said tracking the port comprises at least one of:

generating a flag indicating that the port generates a request to receive a video signal; and

removing the flag upon determining that the port does not generate a request to receive a video signal.

31. An optical system comprising:

a plurality of cameras;

a plurality of optical video inputs operationally coupled to said cameras;

a processor operationally coupled to said optical video inputs;

a plurality of optical video outputs coupled to said optical video inputs via said processor, said optical video outputs also coupled to a plurality of video monitors, said processor configured to;

receive video data from at least two of said plurality of optical video inputs;

packetize the received video data;

route the packetized video data to at least two of said plurality of optical video outputs; and

route, by using a video network address (VNA) lookup table, each packet of the packetized video data based upon a VNA contained in each packet of the packetized video data; and

a mapper coupled to said processor and configured to track a port that outputs a request to receive a video signal, wherein said mapper configured to determine a spare capacity of a path between said mapper and the port by obtaining a value indicated within the request to receive the video signal.

32. A system in accordance with claim 31 further comprising a Field Programmable Logic Gate Array (FPGA) operationally coupled to said processor, said FPGA configured to detect a start of field (SOF) data pattern for the packetized video data.

33. A system in accordance with claim 32 wherein said FPGA comprises a pacer circuit configured to pace an output of the routed packetized video data.

34. A system in accordance with claim 33 wherein said pacer circuit configured to:

output the routed packetized video data at a first resolution when the packetized video data is interlaced; and

output the routed packetized video data at a second resolution when the packetized video data is non-interlaced.

35. A system in accordance with claim 33 wherein said pacer circuit configured to:

output the routed packetized video data at a first resolution when the packetized video data is interlaced; and

output the routed packetized video data at a second resolution when the packetized video data is non-interlaced, the second resolution approximately one-half the first resolution.

36. A system in accordance with claim 31 further comprising:

at least one optical audio input operationally coupled to said processor; and

at least one optical audio output operationally coupled to said processor, said processor further configured to packetize audio data received from said optical audio input in a packet of equal size to a packet size of said packetized video data.

37. A system in accordance with claim 36 wherein each said audio packet and each said video packet comprise between twenty bytes per packet and thirty bytes per packet.

38. A system in accordance with claim 37 wherein each said audio packet and each said video packet comprise approximately twenty-five bytes per packet.

39. A system in accordance with claim 37 wherein each said audio packet and each said video packet comprise twenty-five bytes per packet.

40. A system in accordance with claim 31 wherein said plurality of optical video inputs and said plurality of optical video outputs are connected in a linear topology.

41. A system in accordance with claim 31 wherein each said optical video input is configured to:

receive an analog video input from an analog video source; and

output to said processor an optical digital video signal.

42. A system in accordance with claim 31 wherein each optical video output is configured to:

receive from said processor an optical digital video signal; and

output an analog video signal.

43. A system in accordance with claim 31 wherein said plurality of optical video inputs and said plurality of optical video outputs are connected in a tree topology.

44. A system in accordance with claim 31 wherein each VNA comprises thirteen bits.

45. A optical multiplexer comprising:

a plurality of inputs;

a processor operationally coupled to said inputs; and

a plurality of optical outputs coupled to said inputs via said processor, said processor configured to;

receive data from at least two of said plurality of inputs;

packetize the received data;

route the packetized data to at least two of said plurality of optical outputs; and

determine whether a first one of a plurality of nodes of a network including said processor generates a broadcast configured to receive video signals from a second one of the nodes, wherein the second one of the nodes transmits the video signals in response to the broadcast; and

a mapper coupled to said processor and configured to determine a spare capacity of a path between said mapper and a port that outputs a request to receive a video signal, wherein said mapper configured to determine the spare capacity by obtaining a value indicated within the request to receive the video signal.

46. A multiplexer in accordance with claim 45 wherein said multiplexer is operating a synchronous optical network.

47. A multiplexer in accordance with claim 46 where said optical inputs operationally coupled to at least one of an analog source and a digital source.

48. A multiplexer in accordance with claim 46 wherein said optical inputs operationally coupled to at least one optical source.

49. A multiplexer in accordance with claim 46 wherein said inputs are configured to receive an analog input and convert the analog input to an optical signal and send the optical signal to said processor.

50. A multiplexer in accordance with claim 49 wherein said processor further configured to send the converted optical signal to said optical outputs which convert the optical signal to a non-optical signal.

51. A multiplexer in accordance with claim 45, said processor further configured to determine an amount of network bandwidth available to the nodes other than the first node based on said determining whether the first one of the nodes generates the broadcast.