Maintaining synchronization between frame control word and data frame pairs in a home network

• US 7,133,423 B1
• Filed: 06/19/2001
• Issued: 11/07/2006
• Est. Priority Date: 06/19/2001
• Status: Active Grant

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Chow, Peter K., Gaspar, Harand
• Primary Examiner(s): Ngo, Ricky Q.
• Assistant Examiner(s): CHANG, RICHARD K
• Application Number:
  US09/884,660
• Time in Patent Office: 1,967 Days
• Field of Search: 370/445, 370/446, 370/419, 370/420, 370/469, 370/503, 370/504, 370/509
• US Class Current: 370/504
• CPC Class Codes: H04J 3/0685 Clock or time synchronisation in a node; Intranode synchronisation
• CPC Class Codes: H04L 2007/045 Fill bit or bits, idle words

Abstract

A method and system for maintaining synchronization in a home network is disclosed. The home network includes a host ethernet media access controller and an HPNA chip, where control frame and data frame pairs are transferred between the host ethernet media access controller (MAC) and the HPNA chip. The method and system include sending a null frame from the host ethernet MAC to the HPNA chip prior to the data frame, and recognizing the null frame on the HPNA chip as an indication that a next received frame will be the data frame, thereby maintaining synchronization between the control frame and the data frame pairs.

Claims

1. A method for maintaining synchronization in a home network that includes a host Ethernet media controller and an HPNA chip, where control frame and data frame pairs are transferred between the host Ethernet media access controller (MAC) and the HPNA chip, the method comprising the steps of:

(a) sending a null frame from the host Ethernet MAC to the HPNA chip prior to the data frame; and

(b) recognizing the null frame on the HPNA chip as an indication that a next received frame will be the data frame, thereby maintaining synchronization between the control frame and the data frame pairs.

2. A method for maintaining synchronization in a home network that includes a host Ethernet media controller and an HPNA chip, where control frame and data frame pairs are transferred between the host Ethernet media access controller (MAC) and the HPNA chip, the method comprising the steps of:

(a) sending a null frame from the host Ethernet MAC to the HPNA chip prior to the data frame; and

(b) recognizing the null frame on the HPNA chip as an indication that a next received frame will be the data frame, thereby maintaining synchronization between the control frame and the data frame pairs;

wherein the null frame includes a source address field and an Ethernet type field, step (a) further including the step of providing an invalid address in the source address field and the Ethernet type field.

3. The method of claim 2 wherein step (a) further includes the step of providing all-zeros in the source address field and the Ethernet type field.

4. The method of claim 2 wherein step (a) further includes the step of providing the null frame as a minimum size Ethernet frame.

5. The method of claim 2 wherein step (a) further includes the step of issuing from the host Ethernet MAC a minimum size frame containing a frame control word prior to the data frame during a transmit sequence.

6. The method of claim 2 wherein step (a) further includes the step of issuing from the HPNA chip a minimum size frame containing a frame status word with the data frame during a receive sequence.

7. The method of claim 2 wherein the null frame further includes a destination address field, step (a) further including the step of providing the destination address with a destination address of a corresponding frame received during a receive sequence.

8. A system for maintaining synchronization in a home network that includes a host Ethernet media access controller and an HPNA chip, wherein control frame and data frame pairs are transferred between the host Ethernet media access controller (MAC) and the HPNA chip, the system comprising:

(a) means for sending a null frame from the host Ethernet MAC to the HPNA chip prior to the data frame; and

(b) means for recognizing the null frame on the HPNA chip as an indication that a next received frame will be the data frame, thereby maintaining synchronization between the control frame and the data frame pairs.

9. A system for maintaining synchronization in a home network that includes a host Ethernet media access controller and an HPNA chip, wherein control frame and data frame pairs are transferred between the host Ethernet media access controller (MAC) and the HPNA chip, the system comprising:

(a) means for sending a null frame from the host Ethernet MAC to the HPNA chip prior to the data frame; and

(b) means for recognizing the null frame on the HPNA chip as an indication that a next received frame will be the data frame, thereby maintaining synchronization between the control frame and the data frame pairs;

wherein the null frame includes a source address field and an Ethernet type field that contains an invalid address.

10. The system of claim 9 wherein the source address field and the Ethernet type field contain all-zeros.

11. The system of claim 9 wherein the null frame comprises a minimum size Ethernet frame.

12. The system of claim 9 wherein the host Ethernet MAC issues a minimum size frame containing a frame control word prior to the data frame during a transmit sequence.

13. The system of claim 9 wherein the HPNA chip issues a minimum size frame containing a frame status word with the data frame during a receive sequence.

14. The system of claim 9 wherein the null frame further includes a destination address field that contains a destination address of a corresponding frame received during a receive sequence.

15. A method for maintaining synchronization in a home network that includes a host Ethernet media access controller program and media interface of an HPNA chip, where control frame and data frame pairs are transferred between the host Ethernet media access controller (MAC) and the HPNA chip, the method comprising the steps of:

(a) sending a null frame having a source address field and an Ethernet type field from the host Ethernet MAC to the media interface prior to the data frame, wherein the source address field and the Ethernet type field in the null frame include all zeros; and

(b) in response to receiving the null frame by the media interface, recognizing the zeros in the source address field and the Ethernet type field as an indication that a next received frame will be the data frame, thereby maintaining synchronization between the control frame and the data frame pairs.

16. The method of claim 15 wherein step (a) further includes the step of providing the null frame as a minimum size Ethernet frame.

17. The method of claim 16 wherein step (a) further includes the step of issuing from the host Ethernet MAC the null frame containing a frame control word prior to the data frame during a transmit sequence.

18. The method of claim 17 wherein step (a) further includes the step of issuing from the HPNA chip the null frame containing a frame status word with the data frame during a receive sequence.

19. The method of claim 18 wherein the null frame further includes a destination address field, step (a) further including the step of providing the destination address with a destination address of a corresponding frame received during a receive sequence.

20. A home network, comprising:

a host Ethernet media access controller (MAC);

an HPNA chip having a media interface in communication with the host Ethernet MAC; and

control frame and data frame pairs transferred between the host Ethernet MAC and the HPNA chip, wherein the control frame includes a source address field and an Ethernet type field,

wherein synchronicity is maintained between the control frame and data frame pairs by placing an invalid address in the source address field and the Ethernet type field of the control frame, such that the invalid address indicates to a receiver of the control frame that a next received frame will be the data frame.

21. The system of claim 20 wherein the invalid address comprises all zeros.

22. The system of claim 20 wherein the null frame comprises a minimum size Ethernet frame.

23. The system of claim 21 wherein the host Ethernet MAC issues a minimum size frame containing a frame control word prior to the data frame during a transmit sequence.

24. The system of claim 22 wherein the HPNA chip issues a minimum size frame containing a frame status word with the data frame during a receive sequence.

25. The system of claim 23 wherein the null frame further includes a destination address field that contains a destination address of a corresponding frame received during a receive sequence.