Acquisition method and apparatus for carrying out the method

• US 7,133,438 B2
• Filed: 01/22/2001
• Issued: 11/07/2006
• Est. Priority Date: 07/21/1998
• Status: Expired due to Fees

• Current Assignee: Intel Deutschland GmbH (Intel Corporation)
• Original Assignee: Infineon Technologies AG
• Inventors: Gunzelmann, Bertram, Molev-Shteiman, Arkadi
• Primary Examiner(s): Tran, Khanh
• Assistant Examiner(s): Ahn, Sam K.
• Application Number:
  US09/767,379
• Publication Number:
  US 20010030994A1
• Time in Patent Office: 2,115 Days
• Field of Search: 375/150, 375/147, 375/151, 375/130, 375/136, 375/343, 375/316, 375/152
• US Class Current: 375/150
• CPC Class Codes: H04B 1/708 Parallel implementation
• CPC Class Codes: H04B 1/7095 Sliding correlator type

Abstract

Communications acquisition method for correlating an incoming binary-coded spread sequence having m bits and arriving at a frequency f with a locally generated spread sequence by phase-shifting a multiplicity of locally generated spread sequences with respect to the received spread sequence. The received spread sequence being correlated with a locally generated spread sequence at the frequency f. The received spread sequence is stored. The received, stored spread sequence is split into sections and the correlation is carried out in steps at an oversampling rate. A correlator includes a shift register with feedback. Register positions of the shift register are connected in parallel to a memory input, and the memory output is connected in parallel with the register positions. A further memory holds reference signal sequences and another comparator compares the memory content with further memory content.

Claims

1. A correlator for performing a communications acquisition, comprising:

a FIFO memory having a memory input and a memory output, said FIFO memory inputting and outputting a content;

a shift register with feedback for holding a received signal sequence in serial form, said shift register having register positions connected in parallel to said memory input for parallel storage of a plurality of shift register contents read out in succession, said memory output being connected in parallel with said register positions for parallel transfer of data to said shift register;

a further memory for holding reference signal sequences; and

a comparator for comparing the content of said FIFO memory with a content of said further memory;

the correlator programmed to perform the step of;

correlating a binary-coded spread sequence arriving at a frequency f and having m bits with a locally generated spread sequence by

storing the received binary-coded spread sequence;

splitting the stored received binary-coded spread sequence into k sections; and

correlating the sections of the stored received binary-coded spread sequence at a frequency of k*f with corresponding sections of the locally generated spread sequence.

2. The correlator according to claim 1, wherein said comparator has a comparator output, and including an adder comprising two-bit adders configured to form a cascaded interconnection, each of said two-bit adders having at least two inputs and an output, said output of each of said two-bit adders connected to one of said at least two inputs of a succeeding one of said two-bit adders, said adder connected to said comparator output and configured to add up logic values produced during bit-by-bit comparison for matching bit positions.