Level shifter

• US 7,133,487 B2
• Filed: 11/02/2004
• Issued: 11/07/2006
• Est. Priority Date: 12/22/2003
• Status: Expired due to Fees

• Current Assignee: Sunplus Technology Co., Ltd
• Original Assignee: Sunplus Technology Co., Ltd
• Inventors: Lin, Kun Tsung
• Primary Examiner(s): Tran, Anh Q.
• Application Number:
  US10/978,364
• Publication Number:
  US 20050134311A1
• Time in Patent Office: 735 Days
• Field of Search: 326/68, 326 80- 81, 327/333
• US Class Current: 326/68
• CPC Class Codes: H03K 17/102 in field-effect transistor switches
• CPC Class Codes: H03K 3/012 Modifications of generator to improve response time or to decrease power consumption
• CPC Class Codes: H03K 3/356113 using additional transistors in the input circuit

Abstract

A level shifter has a pair of P-type MOS transistor switches, a pair of N-type MOS transistor switches, an inverter and a plurality of triggers. The triggers are connected to gates of high-voltage devices (N-type MOS transistor switches) and substrates of the high-voltage devices, so that the triggers can produce a trigger signal for a period of time after receiving a low voltage control signal in order to change voltages on the substrates at transition and further reduce threshold voltages of the substrates to increase transition speed of the shifter circuit.

Claims

1. A level shifter, comprising:

a first switch circuit having a first switch and a second switch, each having a first terminal, a second terminal and a third terminal, wherein the first terminals of the first and the second switches are connected to a high voltage node;

a second switch circuit having a third switch and a fourth switch, each having a fourth terminal, a fifth terminal and a sixth terminal, wherein the fourth terminal of the third switch is connected to the third terminal of the first switch and the second terminal of the second switch, the fourth terminal of the fourth switch is connected to the second terminal of the first switch and the third terminal of the second switch, the sixth terminals of the third and the fourth switches are connected to a low voltage node, the fifth terminal of the third switch receives an input control signal and the fifth terminal of the fourth switch receives an inverted input control signal; and

first and second triggers having a delay unit, an inverter and an AND gate respectively and connected across the third and the fourth switches for dynamically changing respective substrate voltages of the third and the fourth switches, thereby reducing respective threshold voltages of the third and the fourth switches and turning on respective parasitic bipolar junction transistors (BJTs) on the third and the fourth switches.

2. The level shifter as claimed in claim 1, wherein the first and second triggers respectively receive the input control signal and the inverse signal, and produce a respective trigger signal for a predetermined interval, thereby changing respective substrate voltages of the third and the fourth switches as the level shifter is at transition.

3. The level shifter as claimed in claim 1, wherein the first trigger changes a substrate voltage of the third switch to increase current and transition speed of the third switch.

4. The level shifter as claimed in claim 1, wherein the second trigger changes a substrate voltage of the fourth switch to increase current and transition speed of the fourth switch.

5. The level shifter as claimed in claim 1, wherein substrate voltages changed on the third and the fourth switches are the same.

6. The level shifter as claimed in claim 1, wherein substrate voltages changed on the third and the fourth switches are different.

7. The level shifter as claimed in claim 1, further comprising a fifth switch coupled between the first and the third switches, and a sixth switch coupled between the second and the fourth switches, thereby providing a function of current limit.

8. The level shifter as claimed in claim 7, wherein the fifth and the sixth switches have a seventh terminal, an eighth terminal and a ninth terminal respectively, the seventh terminal of the fifth switch connected to the third terminal of the first switch, the ninth terminal of the fifth switch connected to the fourth terminal of the third switch, the seventh terminal of the sixth switch and the third terminal of the second switch, and the ninth terminal of the sixth switch and the fourth terminal of the fourth switch.

9. The level shifter as claimed in claim 7, wherein the first, the second, the fifth and the sixth switches are PMOS transistors, and the third and the fourth switches are NMOS transistors.

10. A level shifter, comprising:

a first switch circuit having a plurality of first switches connected to a first voltage node;

a second switch circuit having a plurality of second switches connected to a second voltage node,

wherein when the first voltage node is a high voltage node and the second voltage node is a low voltage node, the second switch circuit is connected to a trigger having a delay unit, an inverter and an AND gate, the second switch circuit and the trigger receive a low voltage control signal respectively for the second switches to switch and further invoke the first switches to switch, the trigger produces a trigger signal for a predetermined interval such that substrate voltage of at least one second switch is changed when the first switch circuit and the second switch circuit are at transition, thereby reducing a threshold voltage of the at least one second switch and increasing circuit transition speed to output a high voltage control signal.

11. The level shifter as claimed in claim 10, wherein the first voltage node is a low positive voltage node and the second voltage node is a high negative voltage node, the first switch circuit is connected to a first trigger having a delay unit, an inverter and an AND gate, the first switch circuit and the first trigger receive a low voltage control signal respectively for the first switches to switch and further invoke the second switches to switch, and the first trigger produces a trigger signal for a predetermined time such that substrate voltage of at least one first switch is changed when the first switch circuit and the second switch circuit are at transition.

12. The level shifter as claimed in claim 10, further comprising third and fourth switches coupled between the first and the second switch circuits, thereby providing a function of current limit.

13. The level shifter as claimed in claim 12, wherein the first switches, the third switch and the fourth switch are P-type MOS transistors, and the second switches are N-type MOS transistors.

14. A level shifter, comprising:

a first switch circuit having a first switch and a second switch, each having a first terminal, a second terminal and a third terminal, wherein the first terminals of the first and the second switches are connected to a high voltage node;

a second switch circuit having a third switch and a fourth switch, each having a fourth terminal, a fifth terminal and a sixth terminal, wherein the fourth terminal of the third switch is connected to the third terminal of the first switch and the second terminal of the second switch, the fourth terminal of the fourth switch is connected to the second terminal of the first switch and the third terminal of the second switch, the sixth terminals of the third and the fourth switches are connected to a low voltage node, the fifth terminal of the third switch receives an input control signal and the fifth terminal of the fourth switch receives an inverted input control signal; and

first and second triggers which are respectively an RC delay circuit consisting of a resistor and a capacitor and connected across the third and the fourth switches for dynamically changing respective substrate voltages of the third and the fourth switches, thereby reducing respective threshold voltages of the third and the fourth switches and turning on respective parasitic bipolar junction transistors (BJTs) on the third and the fourth switches.

15. The level shifter as claimed in claim 14, wherein the first and second triggers respectively receive the input control signal and the inverse signal, and produce a respective trigger signal for a predetermined interval, thereby changing respective substrate voltages of the third and the fourth switches as the level shifter is at transition.

16. The level shifter as claimed in claim 14, wherein the first trigger changes a substrate voltage of the third switch to increase current and transition speed of the third switch.

17. The level shifter as claimed in claim 14, wherein the second trigger changes a substrate voltage of the fourth switch to increase current and transition speed of the fourth switch.

18. The level shifter as claimed in claim 14, wherein substrate voltages changed on the third and the fourth switches are the same.

19. The level shifter as claimed in claim 14, wherein substrate voltages changed on the third and the fourth switches are different.

20. The level shifter as claimed in claim 14, further comprising a fifth switch coupled between the first and the third switches, and a sixth switch coupled between the second and the fourth switches, thereby providing a function of current limit.

21. The level shifter as claimed in claim 20, wherein the fifth and the sixth switches have a seventh terminal, an eighth terminal and a ninth terminal respectively, the seventh terminal of the fifth switch connected to the third terminal of the first switch, the ninth terminal of the fifth switch connected to the fourth terminal of the third switch, the seventh terminal of the sixth switch and the third terminal of the second switch, and the ninth terminal of the sixth switch and the fourth terminal of the fourth switch.

22. The level shifter as claimed in claim 20, wherein the first, the second, the fifth and the sixth switches are PMOS transistors, and the third and the fourth switches are NMOS transistors.

23. A level shifter, comprising:

a first switch circuit having a plurality of first switches connected to a first voltage node;

a second switch circuit having a plurality of second switches connected to a second voltage node,

wherein when the first voltage node is a high voltage node and the second voltage node is a low voltage node, the second switch circuit is connected to a trigger which is an RC delay circuit consisting of a resistor and a capacitor, the second switch circuit and the trigger receive a low voltage control signal respectively for the second switches to switch and further invoke the first switches to switch, and the trigger produces a trigger signal for a predetermined interval such that substrate voltage of at least one second switch is changed when the first switch circuit and the second switch circuit are at transition, thereby reducing a threshold voltage of the at least one second switch and increasing circuit transition speed to output a high voltage control signal.

24. The level shifter as claimed in claim 23, wherein the first voltage node is a low positive voltage node and the second voltage node is a high negative voltage node, the first switch circuit is connected to a first trigger which is a RC delay circuit consisting of a resistor and a capacitor, the first switch circuit and the first trigger receive a low voltage control signal respectively for the first switches to switch and further invoke the second switches to switch, and the first trigger produces a trigger signal for a predetermined time such that substrate voltage of at least one first switch is changed when the first switch circuit and the second switch circuit are at transition.

25. The level shifter as claimed in claim 23, further comprising third and fourth switches coupled between the first and the second switch circuits, thereby providing a function of current limit.

26. The level shifter as claimed in claim 25, wherein the first switches, the third switch and the fourth switch are P-type MOS transistors, and the second switches are N-type MOS transistors.