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Chiprate correction in digital transceivers

  • US 7,133,647 B2
  • Filed: 09/23/2002
  • Issued: 11/07/2006
  • Est. Priority Date: 09/23/2002
  • Status: Active Grant
First Claim
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1. A wireless transceiver comprising:

  • a receiver to receive coded information signals;

    a transmitter to transmit coded information signals;

    a local oscillator providing a time and frequency reference for said receiver and said transmitter;

    a timing controller providing timing signals for said receiver and said transmitter;

    a signal processor to decode said coded information signals received by said receiver and to determine a timing error associated with said timing controller based on said received coded information signals; and

    an automatic frequency control circuit outputting a control signal to said local oscillator responsive to a frequency error to adjust the frequency reference output by said local oscillator, said automatic frequency control circuit including an integrator to integrate said frequency error to generate said control signal;

    a timing correction circuit to smoothly adjust timing of said coded information transmitted by said transmitter responsive to said timing error to reduce said timing error over a desired time interval, said timing control circuit comprising;

    a timing correction loop to generate a frequency offset value based on said timing error that modifies the frequency error so as to bias the frequency reference output by said local oscillator in a manner to reduce the timing error,a scaling and filtering unit to smooth the timing error over a predetermined period of time;

    an integrator to integrate said timing error to generate said frequency offset value to produce an increasing frequency bias as long as the sign of the timing error remains the same.

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