Method for adaptive critical path delay estimation during timing-driven placement for hierarchical programmable logic devices

• US 7,133,819 B1
• Filed: 02/13/2001
• Issued: 11/07/2006
• Est. Priority Date: 08/24/2000
• Status: Expired due to Fees

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Hutton, Michael D.
• Primary Examiner(s): Rodriquez, Paul L.
• Assistant Examiner(s): STEVENS, THOMAS H
• Application Number:
  US09/783,246
• Time in Patent Office: 2,093 Days
• Field of Search: 703 19- 20, 703/121, 716/2, 716/4, 716 7- 14, 716 16- 18, 716/6, 716/5, 326 39- 41
• US Class Current: 703/19
• CPC Class Codes: G06F 30/3312 Timing analysis
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement

Abstract

Provided is a method for estimating delay data comprising receiving an electronic representation of a source electronic design, estimating the criticality of connections which have not yet been placed across a boundary based on statistical data received from at least one other design and revising the design in a manner that biases the design towards a state in which connections with the highest criticality have their delays minimized. A statistical estimate is generated for uncut connections on a path in a partially placed source design comprising receiving at least one source design, partitioning the design, and generating statistical data corresponding to each type of partitioning cut.

Claims

1. A method of estimating a critical path delay during a source electronic design placement into a target hardware device, comprising:

receiving an electronic representation of the source electronic design;

determining a path criticality in the source electronic design based on,

determining an actual delay corresponding to a connection already placed across a first boundary in the target device, and

determining a statistical estimate for a future delay corresponding to an associated future connection to be placed across a second boundary in the target device, wherein the statistical estimate for the future delay is made using estimates of future cuts not yet made in the target device; and

partitioning at least a portion of the source design by placing at least the portion of the source design across boundaries in the target device based on the determined actual delay and the statistical estimate for a future delay.

2. The method of claim 1 wherein the placing is biased towards a state in which an individual path having a relatively high criticality is not changed so as to increase an associated delay.

3. The method of claim 1 wherein the placing is biased towards a state in which an individual path having a relatively high criticality is changed in a manner that reduces the associated delay.

4. The method of claim 2 wherein the estimate for the future delay is generated by performing partitioning techniques on at least one other electronic source design.

5. The method of claim 1 wherein the electronic representation is received in the form of hardware description language coding.

6. The method of claim 1 wherein the electronic representation is received in the form of a schematic electronically captured.

7. The method of claim 1 wherein the electronic representation is received in the form selected from a group comprising:

a netlist, an electronically captured schematic, and a coded hardware description language.

8. The method of claim 1 wherein the connections include at least one of conductive lines and switches.

9. The method of claim 1 wherein the target hardware device is selected from a group comprising:

a complex programmable logic device (CPLD), a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a programmable logic device, a general purpose microprocessor, and a board level circuit implementation.

10. The method of claim 1 further comprising iteratively repeating the determining a path criticality and the partitioning at least a portion of the source design.

11. The method of claim 1, further comprising:

determining whether to repartition the at least a portion of the source design after the partitioning; and

if necessary, adjusting the estimates of delays from future partitions.

12. The method of claim 11 wherein determining whether to repartition at least a portion of the source electronic design is determined by comparing the critical path delays resulting from the partitioning cut with the estimate of critical path delays prior to the partitioning cut.

13. The method of claim 10 wherein adjusting the estimates of delays from future partitions comprises:

substituting a percentage of delays attributed to the partition in the statistical estimate with a new percentage derived from the critical path delay results from the partitions.

14. The method of claim 1 wherein the statistical estimate for future delay comprises:

receiving at least one source design;

placing the at least one source design using partitioning methods to place the device across boundaries in the target device; and

generating statistical data corresponding to each type of boundary crossed in the target device.

15. The method of claim 14 wherein the statistical data represents the proportion of each hierarchical type of cut of the entire number of cuts in the fully placed design.

16. The method of claim 15 is wherein the statistical estimates correspond to the weighted average of the statistical data generated.

17. The method of claim 16 wherein the weighted average is based on a predetermined number or percentage of the slowest delays.

18. The method of claim 16 wherein the weighted average is based on a predetermined number or percentage of the fastest delays.

19. A method for generating statistical estimates for future delays on uncut connections on a path in placing a design by partitioning methods comprising:

receiving at least one source design;

placing the at least one source design using partitioning methods to place the device across boundaries in the target device; and

generating statistical data corresponding to each type of boundary crossed in the target device, wherein the statistic data is generated using estimates of future cuts not yet made in the target device.

20. The method of claim 19 wherein the statistical data represents the proportion of each hierarchical type of cut of the entire number of cuts in the fully placed design.

21. The method of claim 19 wherein the statistical estimates correspond to the weighted average of the statistical data generated.

22. The method of claim 21 wherein the weighted average is based on a predetermined number or percentage of the slowest delays.

23. The method of claim 21 wherein the weighted average is based on a predetermined number or percentage of the fastest delays.

24. A computer program product comprising:

a machine readable memory on which is provided program instructions for a method of placing a source electronic design into a target hardware device by partitioning methods, the instructions comprising;

code for receiving an electronic representation of the source electronic design;

code for determining a path criticality in the source electronic design based on determining an actual delay corresponding to a connection already placed across a first boundary in the target device,

code for determining a statistical estimate for a future delay corresponding to an associated future connection to be placed across a second boundary associated with a future cut not yet made in the target dance; and

code for partitioning at least a portion of the source design by placing the at least a portion of the source design across boundaries in the target device based on the criticalities determined.

25. The computer program product of claim 24 wherein the code for determining the statistical estimate for future delay comprises:

code for receiving at least one source design;

code for placing the at least one source design using partitioning methods to place the device across boundaries in the target device; and

code for generating statistical data corresponding to each type of boundary crossed in the target device.

26. The computer program product of claim 25 wherein the statistical data represents the proportion of each hierarchical type of cut of the entire number of cuts in the fully placed design.

27. The computer program product of claim 26 wherein the statistical estimates correspond to the weighted average of the statistical data generated.

28. The computer program product of claim 27 wherein the weighted average is based on a predetermined number or percentage of the slowest delays.

29. The computer program product of claim 28 wherein the weighted average is based on a predetermined number or percentage of the fastest delays.

30. A computer system having a central processing unit (CPU) coupled to a memory, comprising:

an interface for communicating with an individual;

wherein the computer system is configured to receive an electronic representation of the source electronic design;

wherein the computer system is further configured to,

determine a path criticality in the source electronic design based on determining an actual delay corresponding to a connection already placed across a first boundary in the target device, and

determine a statistical estimate for a fixture delay corresponding to an associated future connection to be placed across a second boundary associated with a fixture cut not yet made in the target device; and

wherein the computer system is further configured to partition at least a portion of the source design by placing the at least a portion of the source design across boundaries in the target device based on the determined actual delay.