Memory hub with internal cache and/or memory access prediction

• US 7,133,972 B2
• Filed: 06/07/2002
• Issued: 11/07/2006
• Est. Priority Date: 06/07/2002
• Status: Expired due to Fees

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Jeddeloh, Joseph M.
• Primary Examiner(s): Bataille, Pierre-Michel
• Application Number:
  US10/165,787
• Publication Number:
  US 20030229770A1
• Time in Patent Office: 1,614 Days
• Field of Search: 711/119, 711/118, 711/112, 711/113, 711/154, 711/137, 711/114, 710/36, 710/23, 710/22, 710/3, 710/100, 709/104, 709/233, 709/229
• US Class Current: 711/137
• CPC Class Codes: G06F 12/0862 with prefetch
• CPC Class Codes: G06F 12/0866 for peripheral storage systems, e.g. disk cache
• CPC Class Codes: G06F 12/0893 Caches characterised by their organisation or structure
• CPC Class Codes: G06F 13/161 with latency improvement

Abstract

A computer system includes a memory hub for coupling a processor to a plurality of synchronous dynamic random access memory (“SDRAM”) devices. The memory hub includes a processor interface coupled to the processor and a plurality of memory interfaces coupled to respective SDRAM devices. The processor interface is coupled to the memory interfaces by a switch. Each of the memory interfaces includes a memory controller, a cache memory, and a prediction unit. The cache memory stores data recently read from or written to the respective SDRAM device so that it can be subsequently read by processor with relatively little latency. The prediction unit prefetches data from an address from which a read access is likely based on a previously accessed address.

Claims

1. A memory hub, comprising:

a memory access device interface structured to interface with a memory access device;

a plurality of memory interfaces structured to interface with respective memory devices, each of the memory interfaces comprising;

a memory controller;

a cache memory; and

a prediction unit structured to predict an address from which data are likely to be read based on an address from a prior memory access and to cause the memory controller in the respective memory interface to output signals indicative of a memory read operation from the predicted address; and

a switch coupling the memory access device interface to each of the memory interfaces.

2. The memory hub of claim 1 wherein the memory access device interface comprises a processor interface structured to interface with a processor.

3. The memory hub of claim 1 wherein the prediction unit is further structured to cause the memory interface to store in the cache memory read data received responsive to the signals indicative of a memory read operation.

4. The memory hub of claim 1 wherein each of the memory interfaces operates at the same clock speed.

5. The memory hub of claim 1 wherein the switch comprises a cross-bar switch.

6. The memory hub of claim 1 wherein the switch comprises a multiplexer switch.

7. The memory hub of claim 1 wherein the cache memory comprises dynamic random access memory.

8. A memory hub, comprising:

a memory access device interface structured to interface with a memory access device;

a plurality of memory interfaces structured to interface with respective memory devices, each of the memory interfaces including a memory controller and a prediction unit structured to predict an address from which data are likely to be read based on an address from a prior memory access and to cause the memory controller in the respective memory interface to output signals indicative of a memory read operation from the predicted address; and

a switch coupling the memory access device interface to the memory interfaces.

9. The memory hub of claim 8 wherein the memory access device interface comprises a processor interface.

10. The memory hub of claim 8 wherein each of the memory interfaces operates at the same clock speed.

11. The memory hub of claim 8 wherein the switch comprises a cross-bar switch.

12. The memory hub of claim 8 wherein the switch comprises a multiplexer switch.

13. A computer system, comprising:

processing unit operable to perform computing functions;

a system controller coupled to the processing unit;

at least one input device coupled to the processing unit through the system controller;

at least one output device coupled to the processing unit through the system controller;

at least one data storage devices coupled to the processing unit through the system controller;

a plurality of memory devices; and

a memory hub comprising;

a processor interface coupled to the processing unit;

a plurality of memory interfaces coupled to respective ones of the memory devices, each of the memory interfaces comprising;

a memory controller;

a cache memory; and

a prediction unit structured to predict an address from which data are likely to be read based on an address from a prior memory access and to cause the memory controller in the respective memory interface to apply to the memory device to which the memory interface is coupled output signals indicative of a memory read operation from the predicted address; and

a switch coupling the processor interface to each of the memory interfaces.

14. The computer system of claim 13 wherein the memory hub is physically included in the system controller.

15. The computer system of claim 13 wherein the plurality of memory devices are physically packaged in a memory module, and wherein the memory hub is physically included in the memory module.

16. The computer system of claim 13 wherein the prediction unit is further structured to cause the memory interface to store in the cache memory read data received from the respective memory device responsive to the signals indicative of a memory read operation.

17. The computer system of claim 13 wherein each of the memory interfaces operates at the same clock speed.

18. The computer system of claim 13 wherein the switch comprises a cross-bar switch.

19. The computer system of claim 13 wherein the switch comprises a multiplexer switch.

20. The computer system of claim 13 wherein the cache memory comprises dynamic random access memory.

21. The computer system of claim 13 wherein each of the memory devices comprises a dynamic random access memory device.

22. The computer system of claim 19 wherein each of the dynamic random access memory device comprises a synchronous dynamic random access memory device.

23. A computer system, comprising:

a processing unit operable to perform computing functions;

a system controller coupled to the processing unit;

at least one input device coupled to the processing unit through the system controller;

at least one output device coupled to the processing unit through the system controller;

at least one data storage devices coupled to the processing unit through the system controller;

a plurality of memory devices; and

a memory hub comprising;

a processor interface coupled to the processing unit;

a plurality of memory interfaces coupled to respective ones of the memory devices, each of the memory interfaces including a memory controller and a prediction unit structured to predict an address from which data are likely to be read based on an address from a prior memory access and to cause the memory controller in the respective memory interface to output to the memory device to which the memory interface is coupled signals indicative of a memory read operation from the predicted address; and

a switch coupling the processor interface to each of the memory interfaces.

24. The computer system of claim 23 wherein the memory hub is physically included in the system controller.

25. The computer system of claim 23 wherein the plurality of memory devices are physically packaged in a memory module, and wherein the memory hub is physically included in the memory module.

26. The computer system of claim 23 wherein each of the memory interfaces operates at the same clock speed.

27. The computer system of claim 23 wherein the switch comprises a cross-bar switch.

28. The computer system of claim 23 wherein the switch comprises a multiplexer switch.

29. The computer system of claim 23 wherein each of the memory devices comprises a dynamic random access memory device.

30. A method of accessing a plurality of memory devices, comprising:

directing a memory access request to a first of a plurality of memory devices coupled to a memory hub;

storing data read from or written to first of the plurality of memory devices in a cache memory located in the memory hub;

subsequently directing a memory read request to the first of the plurality of memory devices;

in response to the memory read request, detecting whether the data corresponding to the memory read request are stored in the cache memory located in the memory hub;

if the data corresponding to the memory read request are determined to be stored in the cache memory located in the memory hub, providing the read data from the cache memory; and

if the data corresponding to the memory read request are determined to be not stored in the cache memory located in the memory hub, providing the read data from the first of the plurality of memory devices.

31. The method of claim 30 further comprising:

predicting an address from which data are likely to be read from the first of the plurality of memory devices based on an address from a prior memory access to the first of the plurality of memory devices;

providing read data from the predicted address in the first of the plurality of memory devices; and

storing the read data from the predicted address in the cache memory in the memory hub.

32. The method of claim 30 wherein the act of storing data read from or written to the first of the plurality of memory devices in a cache memory in the memory hub comprises storing the data read from or written to the first of the plurality of memory devices in a cache memory dedicated to the first of the plurality of memory devices.

33. The method of claim 30 wherein the memory access request on which the prediction was based comprises a read memory access.

34. The method of claim 30 wherein the memory access request on which the prediction was based comprises a write memory access.

35. A method of accessing a plurality of memory devices, comprising:

directing memory access requests to respective addresses in a plurality of memory devices coupled to a memory hub;

within the memory hub, predicting at least one address from which data are likely to be read from at least one of a plurality of memory devices based on the addresses to which the memory access requests were directed; and

providing respective read data from the predicted addresses in the at least one of a plurality of memory devices prior to receiving memory read requests directed to the predicted addresses.

36. The method of claim 35 wherein the memory access requests on which the predictions were based comprise read memory requests.

37. The method of claim 35 wherein the memory access requests on which the predictions were based comprise write memory requests.