Method and apparatus for processing data stored in a memory shared among a plurality of processors

• US 7,133,978 B1
• Filed: 06/19/2003
• Issued: 11/07/2006
• Est. Priority Date: 06/19/2003
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Ross, Charles A., Schumacher, Paul R., James-Roxby, Philip B.
• Primary Examiner(s): Padmanabhan, Mano
• Assistant Examiner(s): Walter, Craig E
• Application Number:
  US10/600,851
• Time in Patent Office: 1,237 Days
• Field of Search: 711/163, 711/151, 365/38
• US Class Current: 711/152
• CPC Class Codes: G06F 12/1425 the protection being physical, e.g. cell, word, block
• CPC Class Codes: G06F 2209/521 Atomic
• CPC Class Codes: G06F 9/526 Mutual exclusion algorithms

Abstract

Method and apparatus for processing data stored in a memory shared among a plurality of processors is described. In an example, a semaphore is provided that is associated with a first portion of the memory. Tasks are stored in the first portion of the memory, the tasks being respectively related to data segments stored in a second portion of the memory. A state of the semaphore is determined. Access among the plurality of processors to the first portion of the memory is controlled in response to the state of the semaphore. A task is executed to process a data segment of the data segments in response to a processor of the plurality of processors gaining access to the first portion of the memory.

Claims

1. A method for processing data stored in a memory shared among a plurality of processors, comprising:

providing a semaphore associated with a first portion of the memory;

storing tasks in the first portion of the memory, the tasks respectively related to information associated with a second portion of the memory;

determining a state of the semaphore;

controlling access among the plurality of processors to the first portion of the memory in response to the state of the semaphore; and

executing a task to process at least some of the information within the second portion of the memory in response to a processor of the plurality of processors gaining access to the first portion of the memory;

providing another memory respectively coupled to each of the plurality of processors; and

storing a program in the other memory accessible by each of the plurality of processors, the program capable of executing at least one of the tasks.

2. The method of claim 1, wherein the controlling comprises:

allowing one of the plurality of processors to access the first portion of the memory responsive to the semaphore having a first state value; and

blocking access to all of the plurality of processors to the first portion of the memory responsive to the semaphore having a second state value.

3. The method of claim 1, further comprising coupling the semaphore to a bus shared by each of the plurality of processors.

4. The method of claim 1, wherein the storing comprises:

initializing state of the semaphore to allow access to the first portion of the memory; and

receiving tasks to be executed by the processor of the plurality of processors.

5. A method for processing data stored in a memory shared among a plurality of processors, comprising:

storing task data for one or more tasks;

relating each of the one or more tasks to respective one or more data segments stored in a second portion of the memory;

associating a semaphore with the task data;

controlling access among the plurality of processors to the task data in response to a state of the semaphore; and

executing a task of the one or more tasks to process a respective data segment in response to a processor of the plurality of processors gaining access to the task data;

providing another memory respectively coupled to each of the plurality of processors; and

storing a program in the other memory of each of the plurality of processors, the program capable of executing the task of the one or more tasks.

6. The method of claim 5, wherein the controlling comprises:

allowing one of the plurality of processors to access the task data responsive to the semaphore having a first state value; and

blocking access to all of the plurality of processors to the task data responsive to the semaphore having a second state value.

7. The method of claim 5, wherein the task data comprises a current task of the one or more tasks, a next task to be executed immediately following the current task, and a number of idle processors of the plurality of processors.

8. The method of claim 5, further comprising storing an identifier for the processor that executed the task.

9. The method of claim 5, wherein each of the one or more tasks is related to an identifier indicative of task-type.

10. The method of claim 5, wherein the relating comprises:

storing a respective address of the data segment within the second portion of the memory for each of the one or more tasks; and

storing a length of the data segment respectively associated with each of the one or more tasks.