Design-based monitoring
First Claim
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1. A method for monitoring fabrication of an integrated circuit (IC) on a semiconductor wafer, comprising:
- generating a product design profile (PDP) using an electronic design automation (EDA) tool, the PDP comprising an indication of a site in at least one layer of the IC that is susceptible to a process fault;
fabricating the at least one layer of the IC on the wafer; and
applying a process monitoring tool to perform a measurement at the site in the at least one layer responsively to the PDP.
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Abstract
A method for monitoring fabrication of an integrated circuit (IC) on a semiconductor wafer includes generating a product design profile (PDP) using an electronic design automation (EDA) tool, the PDP comprising an indication of a site in at least one layer of the IC that is susceptible to a process fault. Upon fabricating at least one layer of the IC on the wafer, a process monitoring tool is applied to perform a measurement at the site in at least one layer responsively to the PDP.
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Citations
25 Claims
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1. A method for monitoring fabrication of an integrated circuit (IC) on a semiconductor wafer, comprising:
- generating a product design profile (PDP) using an electronic design automation (EDA) tool, the PDP comprising an indication of a site in at least one layer of the IC that is susceptible to a process fault;
fabricating the at least one layer of the IC on the wafer; and
applying a process monitoring tool to perform a measurement at the site in the at least one layer responsively to the PDP. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
- generating a product design profile (PDP) using an electronic design automation (EDA) tool, the PDP comprising an indication of a site in at least one layer of the IC that is susceptible to a process fault;
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11. A method for monitoring fabrication of an integrated circuit (IC) on a semiconductor wafer, comprising:
- generating a product design profile (PDP) using an electronic design automation (EDA) tool, the PDP comprising an identification of a region in at least one layer of the IC that is characterized by a periodic pattern;
fabricating the at least one layer of the IC on the wafer; and
applying a process monitoring tool to perform a measurement in the region of the at least one layer responsively to the periodic pattern. - View Dependent Claims (12, 13, 14, 15)
- generating a product design profile (PDP) using an electronic design automation (EDA) tool, the PDP comprising an identification of a region in at least one layer of the IC that is characterized by a periodic pattern;
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16. A method for monitoring fabrication of an integrated circuit (IC) on a semiconductor wafer, comprising:
- generating a product design profile (PDP) using an electronic design automation (EDA) tool, the PDP comprising an identification of a plurality of regions in at least one layer of the IC and a respective criticality parameter for each of the regions, indicative of a maximum tolerable defect size in each of the regions;
fabricating at least one layer of the IC on the wafer; and
applying a process monitoring tool to perform a measurement in one or more of the regions in at least one layer responsively to the respective criticality parameter. - View Dependent Claims (17, 18, 19)
- generating a product design profile (PDP) using an electronic design automation (EDA) tool, the PDP comprising an identification of a plurality of regions in at least one layer of the IC and a respective criticality parameter for each of the regions, indicative of a maximum tolerable defect size in each of the regions;
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20. A method for monitoring fabrication of an integrated circuit (IC) on a semiconductor wafer, comprising:
- designing a layout of at least one layer of the IC using an electronic design automation (EDA) tool, at least one layer comprising a structure that is amenable to testing;
generating a product design profile (PDP) using the EDA tool, the PDP comprising information regarding the structure;
fabricating at least one layer of the IC on the wafer; and
applying a process monitoring tool to perform a measurement on the structure in at least one layer, responsively the information in the PDP. - View Dependent Claims (21, 22, 23, 24, 25)
- designing a layout of at least one layer of the IC using an electronic design automation (EDA) tool, at least one layer comprising a structure that is amenable to testing;
Specification