Method for fabricating transistor gate structures and gate dielectrics thereof

• US 7,135,361 B2
• Filed: 12/11/2003
• Issued: 11/14/2006
• Est. Priority Date: 12/11/2003
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Visokay, Mark R., Bu, Haowen, Chambers, James J., Colombo, Luigi, Rotondaro, Antonio L. P.
• Primary Examiner(s): Pham, Thanhha S.
• Application Number:
  US10/734,708
• Publication Number:
  US 20050130442A1
• Time in Patent Office: 1,069 Days
• Field of Search: 438/3, 438/197, 438/199, 438/216, 438/287, 438/591, 438/778, 438/785
• US Class Current: 438/197
• CPC Class Codes: H01L 21/02148 the material containing hafnium, e.g. HfSiOx or HfSiON
• CPC Class Codes: H01L 21/02271 deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition H01L21/02266 takes precedence
• CPC Class Codes: H01L 21/02332 into an oxide layer, e.g. changing SiO to SiON
• CPC Class Codes: H01L 21/02337 treatment by exposure to a gas or vapour
• CPC Class Codes: H01L 21/0234 treatment by exposure to a plasma
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28202 in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
• CPC Class Codes: H01L 21/3144 on silicon
• CPC Class Codes: H01L 21/3162 on a silicon body
• CPC Class Codes: H01L 21/31637 Deposition of Tantalum oxides, e.g. Ta2O5
• CPC Class Codes: H01L 21/31641 Deposition of Zirconium oxides, e.g. ZrO2
• CPC Class Codes: H01L 21/31645 Deposition of Hafnium oxides, e.g. HfO2
• CPC Class Codes: H01L 21/31691 with perovskite structure
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material

Abstract

Methods are disclosed for treating deposited gate dielectric materials, in which the deposited dielectric is subjected to one or more non-oxidizing anneals to densify the material, one or more oxidizing anneals to mitigate material defects, and to a nitridation process to introduce nitrogen into the gate dielectric. The annealing may be performed before and/or after the nitridation to mitigate deposition and/or nitridation defects and to densify the material while mitigating formation of unwanted low dielectric constant oxides at the interface between the gate dielectric and the semiconductor substrate.

Claims

1. A method for treating a deposited high-k gate dielectric layer during fabrication of a semiconductor device, the method comprising:

nitriding a deposited high-k gate dielectric layer prior to forming a gate electrode;

performing a first anneal of the deposited high-k gate dielectric layer in a non-oxidizing ambient prior to nitriding the deposited high-k gate dielectric layer; and

performing a second anneal of the deposited high-k gate dielectric layer in an oxidizing ambient prior to forming a the gate electrode and after nitriding the high-k gate dielectric layer.

2. The method of claim 1, wherein the first anneal is performed at a temperature of about 1000 degrees C. or less.

3. The method of claim 2, wherein the first anneal is performed at a temperature of about 900 degrees C. or less.

4. The method of claim 3, wherein the first anneal is performed at a temperature of about 700 degrees C. or more.

5. The method of claim 3, wherein the non-oxidizing ambient of the first anneal comprises N₂, Ar, He, or Ne.

6. The method of claim 2, wherein the non-oxidizing ambient of the first anneal comprises N2, Ar, He, or Ne.

7. The method of claim 1, wherein the non-oxidizing ambient of the first anneal comprises N2, Ar, He, or Ne.

8. The method of claim 1, wherein the second anneal is performed at a temperature of about 1000 degrees C. or less.

9. The method of claim 8, wherein the second anneal is performed at a temperature of about 700 degrees C. or less.

10. The method of claim 9, wherein the second anneal is performed at a pressure of about 1 Torr or less.

11. The method of claim 9, wherein the second anneal is performed at atmospheric pressure.

12. The method of claim 8, wherein performing the second anneal comprises exposing the high-k gate dielectric layer to an oxidizing liquid solution.

13. The method of claim 12, wherein the oxidizing liquid solution comprises H₂O+H₂O₂.

14. The method of claim 12, wherein the oxidizing liquid solution comprises H₂O+O₃.

15. The method of claim 12, wherein the oxidizing liquid solution is taken from the group consisting of H₂SO₄+H₂O₂+H₂O, H₂SO₄+H₂O, HNO₃+H₂O, HNO₃+H₂O₂+H₂O, HCl+H₂O₂+H₂O, and NH₄OH+H₂O₂+H₂O.

16. The method of claim 8, wherein the second anneal is an oxidizing plasma process.

17. The method of claim 8, wherein the second anneal is an ozone anneal.

18. The method of claim 8, wherein the second anneal is a low temperature anneal with UV excitation in an oxidizing ambient.

19. The method of claim 1, further comprising performing a third anneal in a non-oxidizing ambient after nitriding the deposited high-k dielectric layer.

20. The method of claim 19, wherein the third anneal is performed at a temperature above about 1000 degrees C.

21. The method of claim 20, wherein the non-oxidizing ambient of the third anneal comprises N2, Ar, He, or Ne.

22. The method of claim 19, wherein the non-oxidizing ambient of the third anneal comprises N2, Ar, He, or Ne.

23. The method of claim 19, wherein nitriding the deposited high-k gate dielectric layer comprises performing a nitridation anneal in a nitrogen containing ambient.

24. The method of claim 23, wherein the nitridation anneal is performed at a temperature of about 1000 degrees C. or less and wherein the nitrogen containing ambient comprises NH₃.

25. The method of claim 19, wherein nitriding the deposited high-k gate dielectric layer comprises performing a plasma nitridation process.

26. The method of claim 19, further comprising performing a fourth anneal in an oxidizing ambient after performing the first anneal and prior to nitriding the high-k gate dielectric layer.

27. The method of claim 26, wherein the fourth anneal is performed at a temperature of about 700 degrees C. or less.

28. The method of claim 27, wherein the fourth anneal is preformed at a pressure of about 1 Torr or less.

29. The method of claim 27, wherein the fourth anneal is performed at atmospheric pressure.

30. The method of claim 26, wherein performing the fourth anneal comprises exposing the high-k dielectric layer to an oxidizing liquid solution.

31. The method of claim 26, wherein the oxidizing liquid solution comprises H₂O+H₂O₂.

32. The method of claim 26, wherein the oxidizing liquid solution comprises H₂O+O₃.

33. The method of claim 26, wherein the oxidizing liquid solution is selected from the group consisting of H₂SO₄+H₂O₂+H₂O, H₂SO₄+H₂O, HNO₃+H₂O, HNO₃+H₂O₂+H₂O, HCl+H₂O₂+H₂O, and NH₄OH+H₂O₂+H₂O.

34. The method of claim 26, wherein the fourth anneal is an oxidizing plasma process.

35. The method of claim 26, wherein the fourth anneal is an ozone anneal.

36. The method of claim 26, wherein the fourth anneal is a low temperature anneal with UV excitation in an oxidizing ambient.

37. The method of claim 1, wherein nitriding the deposited high-k gate dielectric layer comprises performing a nitridation anneal in a nitrogen containing ambient.

38. The method of claim 37, wherein the nitridation anneal is performed at a temperature of about 1000 degrees C. or less and wherein the nitrogen containing ambient comprises NH₃.

39. The method of claim 1, wherein nitriding the deposited high-k gate dielectric layer comprises performing a plasma nitridation process.

40. A method of fabricating a transistor gate structure, the method comprising:

depositing a high-k gate dielectric layer above a semiconductor body;

nitriding a deposited high-k gale dielectric layer;

performing a first anneal of the deposited high-k gate dielectric in a non-oxidizing ambient prior to nitriding the deposited high-k gate dielectric layer;

performing a second anneal of the deposited high-k gate dielectric in an oxidizing ambient after nitriding the deposited high-k gate dielectric layer;

forming a gate electrode material layer above the gate dielectric layer after nitriding and after performing the first and second anneals; and

patterning the gate electrode and gate dielectric layers to form a patterned gate structure.