Programmable routing structures providing shorter timing delays for input/output signals

• US 7,135,888 B1
• Filed: 07/22/2004
• Issued: 11/14/2006
• Est. Priority Date: 07/22/2004
• Status: Expired due to Fees

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Hutton, Michael D., Lewis, David
• Primary Examiner(s): Barnie, Rexford
• Assistant Examiner(s): White, Dylan
• Application Number:
  US10/897,770
• Time in Patent Office: 845 Days
• Field of Search: 326 37- 41, 326/47, 326/101
• US Class Current: 326/41
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/11898 Input and output buffer/driver structures
• CPC Class Codes: H03K 19/17744 for input/output signals

Abstract

Techniques are provided for routing signals to and from input/output pads on a programmable chip that reduce signal delay times. A programmable routing structure is provided that is dedicated to routing signals to and from the input/output (I/O) pads. The programmable routing structure can include long conductors that transmit signals across the chip quickly without the delay encountered in shorter routing conductors. Signals can be routed to and from the I/O pads through vertical and horizontal dedicated routing conductors that bypass global routing conductors. The dedicated I/O routing structure allows signals to be driven onto the chip and off chip more quickly can be achieved through standard programmable routing structures. The dedicated I/O routing structure can be depopulated to reduce the number of programmable connections between the individual conductors, decreasing die area requirements.

Claims

1. A programmable logic integrated circuit comprising:

a plurality of I/O pads that allow external access to the integrated circuit;

a plurality of programmable global routing conductors;

a plurality of circuit elements;

programmable dedicated routing conductors coupled to transmit signals between the I/O pads and the circuit elements, bypassing the global routing conductors; and

at least one multiplexer coupling a set of the plurality of I/O pads directly to the programmable dedicated routing conductors.

2. The programmable logic integrated circuit defined in claim 1 wherein the dedicated routing conductors comprise dedicated horizontal and vertical routing conductors that are programmably connectable to each other by programmable logic connections.

3. The programmable logic integrated circuit defined in claim 2 wherein the programmable logic connections between the dedicated vertical routing conductors and the dedicated horizontal conductors are depopulated.

4. The programmable logic integrated circuit defined in claim 1 wherein a first set of the dedicated routing conductors are programmably coupled to the I/O pads and a second set of the dedicated routing conductors are perpendicular to and programmably coupled to the first set of dedicated routing conductors.

5. The programmable logic integrated circuit defined in claim 4 further comprising:

the at least one multiplexer couples the set of I/O pads to the first set of programmable dedicated routing conductors.

7. The programmable logic integrated circuit defined in claim 4 further comprising cross coupled tristate drivers that couple together first and second portions of the second set of the dedicated routing conductors.

8. The programmable logic integrated circuit defined in claim 1 wherein each multiplexer has at least three input terminals coupled to at least three of the I/O pads.

9. The programmable logic integrated circuit according to claim 1 wherein the circuit elements are logic elements that are configurable to implement combinatorial and sequential functions.

6. A programmable logic integrated circuit comprising:

a plurality of I/O pads that allow external access to the integrated circuit;

a plurality of programmable global routine conductors;

a plurality of circuit elements;

programmable dedicated routing conductors coupled to transmit signals between the I/O pads and the circuit elements, bypassing the global routing conductors, a first set of the dedicated routing conductors being programmably coupled to the I/O pads and a second set of the dedicated routing conductors being perpendicular to and programmably coupled to the first set of dedicated routing conductors; and

a set of multiplexers that couples the first set of dedicated routing conductors to the second set of dedicated routing conductors,

wherein some of the set of multiplexers couple I/O pads directly to the second set of dedicated routing conductors.

10. A programmable logic integrated circuit comprising:

rows of programmable logic elements that are configurable to perform combinatorial and sequential functions;

programmable global routing conductors aligned in a first direction and a second direction perpendicular to the first direction;

a plurality of I/O pads of the integrated circuit;

dedicated routing conductors coupled to transmit signals between the I/O pads and the logic elements without routing through the global routing conductors; and

at least one multiplexer coupling a set of the plurality of I/O pads directly to the dedicated routing conductors,

wherein the dedicated routing conductors are aligned in the first and the second directions, and the dedicated routing conductors routed in the first direction are programmably connectable to the dedicated routing conductors routed in the second direction by depopulated programmable logic connections.

11. The programmable logic integrated circuit according to claim 10 wherein a first set of the dedicated routing conductors are programmably coupled to the I/O pads and a second set of the dedicated routing conductors are perpendicular to and programmably coupled to the first set of dedicated routing conductors.

12. The programmable logic integrated circuit according to claim 11 further comprising:

a set of multiplexers that couples the first set of dedicated routing conductors to the second set of dedicated routing conductors,

wherein a subset of the multiplexers couple I/O pads directly to the second set of dedicated routing conductors.

13. A method for forming a programmable logic integrated circuit, the method comprising:

providing pads that allow external access to the programmable logic integrated circuit;

providing a plurality of global vertical and horizontal programmable routing conductors;

providing a plurality of circuit elements;

providing programmable dedicated routing conductors that are coupled to transmit signals between the pads and the circuit elements without routing the signals through the global programmable routing conductors; and

providing multiplexers that couple the pads directly to the dedicated routing conductors.

14. The method according to claim 13 wherein the dedicated routing conductors comprise dedicated horizontal and vertical conductors that are programmably connectable to each other by programmable logic connections.

15. The method according to claim 14 wherein the programmable logic connections between the dedicated vertical routing conductors and the dedicated horizontal conductors are depopulated.

16. The method according to claim 13 wherein each multiplexer has at least three input terminals coupled to at least three of the I/O pads.

17. The method according to claim 13 further comprising:

providing a plurality of tristate drivers coupled between the pads and a subset of the dedicated routing conductors.

18. The method according to claim 13 wherein the circuit elements are memory blocks.

19. The method according to claim 13 wherein the circuit elements are logic blocks that are configurable to perform combinatorial and sequential functions.